net: mtk_eth_soc: add definitions for PCS

As a result of help from Frank Wunderlich to investigate and test, we
know a bit more about the PCS on the Mediatek platforms. Update the
definitions from this investigation.

This PCS appears similar, but not identical to the Lynx PCS.

Although not included in this patch, but for future reference, the PHY
ID registers at offset 4 read as 0x4d544950 'MTIP'.

Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index b52f3b0177efb9ed4db04567d5e58211c9b83f84..589f27ddc401633a9f14f989c4276d79fb313702 100644 (file)
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -466,8 +466,10 @@
 #define ETHSYS_DMA_AG_MAP_PPE  BIT(2)
 
 /* SGMII subsystem config registers */
-/* Register to auto-negotiation restart */
+/* BMCR (low 16) BMSR (high 16) */
 #define SGMSYS_PCS_CONTROL_1   0x0
+#define SGMII_BMCR             GENMASK(15, 0)
+#define SGMII_BMSR             GENMASK(31, 16)
 #define SGMII_AN_RESTART       BIT(9)
 #define SGMII_ISOLATE          BIT(10)
 #define SGMII_AN_ENABLE                BIT(12)
@@ -477,13 +479,18 @@
 #define SGMII_PCS_FAULT                BIT(23)
 #define SGMII_AN_EXPANSION_CLR BIT(30)
 
+#define SGMSYS_PCS_ADVERTISE   0x8
+#define SGMII_ADVERTISE                GENMASK(15, 0)
+#define SGMII_LPA              GENMASK(31, 16)
+
 /* Register to programmable link timer, the unit in 2 * 8ns */
 #define SGMSYS_PCS_LINK_TIMER  0x18
-#define SGMII_LINK_TIMER_DEFAULT       (0x186a0 & GENMASK(19, 0))
+#define SGMII_LINK_TIMER_MASK  GENMASK(19, 0)
+#define SGMII_LINK_TIMER_DEFAULT       (0x186a0 & SGMII_LINK_TIMER_MASK)
 
 /* Register to control remote fault */
 #define SGMSYS_SGMII_MODE              0x20
-#define SGMII_IF_MODE_BIT0             BIT(0)
+#define SGMII_IF_MODE_SGMII            BIT(0)
 #define SGMII_SPEED_DUPLEX_AN          BIT(1)
 #define SGMII_SPEED_MASK               GENMASK(3, 2)
 #define SGMII_SPEED_10                 FIELD_PREP(SGMII_SPEED_MASK, 0)