clk: renesas: r9a07g043: Add TSU clock and reset entry

Add TSU clock and reset entry to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220501083450.26541-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index 21cf82ad7de3a7ce4108742949240e04e3cf6ed6..70b1226cf2947af3c0c71ccffb4851495747b65c 100644 (file)
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -27,6 +27,7 @@ enum clk_ids {
        CLK_PLL2,
        CLK_PLL2_DIV2,
        CLK_PLL2_DIV2_8,
+       CLK_PLL2_DIV2_10,
        CLK_PLL3,
        CLK_PLL3_400,
        CLK_PLL3_533,
@@ -90,6 +91,7 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
        DEF_FIXED(".clk_400", CLK_PLL2_SDHI_400, CLK_PLL2_800, 1, 2),
        DEF_FIXED(".clk_266", CLK_PLL2_SDHI_266, CLK_PLL2_SDHI_533, 1, 2),
        DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8),
+       DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10),
        DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
        DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
        DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
@@ -112,6 +114,7 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
        DEF_DIV("P0", R9A07G043_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A,
                dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
        DEF_FIXED("P0_DIV2", R9A07G043_CLK_P0_DIV2, R9A07G043_CLK_P0, 1, 2),
+       DEF_FIXED("TSU", R9A07G043_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1),
        DEF_DIV("P1", R9A07G043_CLK_P1, CLK_PLL3_DIV2_4,
                DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
        DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G043_CLK_P1, 1, 2),
@@ -240,6 +243,8 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
                                0x594, 0),
        DEF_MOD("gpio",         R9A07G043_GPIO_HCLK, R9A07G043_OSCCLK,
                                0x598, 0),
+       DEF_MOD("tsu_pclk",     R9A07G043_TSU_PCLK, R9A07G043_CLK_TSU,
+                               0x5ac, 0),
 };
 
 static struct rzg2l_reset r9a07g043_resets[] = {
@@ -285,6 +290,7 @@ static struct rzg2l_reset r9a07g043_resets[] = {
        DEF_RST(R9A07G043_GPIO_RSTN, 0x898, 0),
        DEF_RST(R9A07G043_GPIO_PORT_RESETN, 0x898, 1),
        DEF_RST(R9A07G043_GPIO_SPARE_RESETN, 0x898, 2),
+       DEF_RST(R9A07G043_TSU_PRESETN, 0x8ac, 0),
 };
 
 static const unsigned int r9a07g043_crit_mod_clks[] __initconst = {