Merge branch 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm

Pull ARM updates from Russell King:
 "Included in this update are:

   - Patches from Gregory Clement to fix the coherent DMA cases in our
     dma-mapping code.

   - A number of CPU errata updates and fixes.

   - ARM cpuidle improvements from Jisheng Zhang.

   - Fix from Kees for the location of _etext.

   - Cleanups from Masahiro Yamada to avoid duplicated messages during
     the kernel build, and remove CONFIG_ARCH_HAS_BARRIERS.

   - Remove a udelay loop limitation, allowing for faster CPUs to
     calibrate the delay correctly.

   - Cleanup some left-overs from the SW PAN implementation.

   - Ensure that a modified address limit is not visible to exception
     handlers"

* 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm: (21 commits)
  ARM: 8586/1: cpuidle: make arm_cpuidle_suspend() a bit more efficient
  ARM: 8585/1: cpuidle: fix !cpuidle_ops[cpu].init case during init
  ARM: 8561/4: dma-mapping: Fix the coherent case when iommu is used
  ARM: 8561/3: dma-mapping: Don't use outer_flush_range when the L2C is coherent
  ARM: 8560/1: errata: Workaround errata A12 825619 / A17 852421
  ARM: 8559/1: errata: Workaround erratum A12 821420
  ARM: 8558/1: errata: Workaround errata A12 818325/852422 A17 852423
  ARM: save and reset the address limit when entering an exception
  ARM: 8577/1: Fix Cortex-A15 798181 errata initialization
  ARM: 8584/1: floppy: avoid gcc-6 warning
  ARM: 8583/1: mm: fix location of _etext
  ARM: 8582/1: remove unused CONFIG_ARCH_HAS_BARRIERS
  ARM: 8306/1: loop_udelay: remove bogomips value limitation
  ARM: 8581/1: add missing <asm/prom.h> to arch/arm/kernel/devtree.c
  ARM: 8576/1: avoid duplicating "Kernel: arch/arm/boot/*Image is ready"
  ARM: 8556/1: on a generic DT system: do not touch l2x0
  ARM: uaccess: remove put_user() code duplication
  ARM: 8580/1: Remove orphaned __addr_ok() definition
  ARM: get rid of horrible *(unsigned int *)(regs + 1)
  ARM: introduce svc_pt_regs structure
  ...

diff --combined arch/arm/Kconfig
index f0636ec949032276be07527f7f7178d068b8f6c4,1be1022c21e8e48cc518529f15539c980e1e664f..4c445fb9c189fe1d527c086f87a572f876830d73
--- 1/arch/arm/Kconfig
--- 2/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@@ -358,10 -358,10 +358,10 @@@ config ARCH_CLPS711
        bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
        select ARCH_REQUIRE_GPIOLIB
        select AUTO_ZRELADDR
 -      select CLKSRC_MMIO
        select COMMON_CLK
        select CPU_ARM720T
        select GENERIC_CLOCKEVENTS
 +      select CLPS711X_TIMER
        select MFD_SYSCON
        select SOC_BUS
        help
@@@ -1186,6 -1186,60 +1186,60 @@@ config ARM_ERRATA_77302
          loop buffer may deliver incorrect instructions. This
          workaround disables the loop buffer to avoid the erratum.
  
+ config ARM_ERRATA_818325_852422
+       bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
+       depends on CPU_V7
+       help
+         This option enables the workaround for:
+         - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
+           instruction might deadlock.  Fixed in r0p1.
+         - Cortex-A12 852422: Execution of a sequence of instructions might
+           lead to either a data corruption or a CPU deadlock.  Not fixed in
+           any Cortex-A12 cores yet.
+         This workaround for all both errata involves setting bit[12] of the
+         Feature Register. This bit disables an optimisation applied to a
+         sequence of 2 instructions that use opposing condition codes.
+ 
+ config ARM_ERRATA_821420
+       bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
+       depends on CPU_V7
+       help
+         This option enables the workaround for the 821420 Cortex-A12
+         (all revs) erratum. In very rare timing conditions, a sequence
+         of VMOV to Core registers instructions, for which the second
+         one is in the shadow of a branch or abort, can lead to a
+         deadlock when the VMOV instructions are issued out-of-order.
+ 
+ config ARM_ERRATA_825619
+       bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
+       depends on CPU_V7
+       help
+         This option enables the workaround for the 825619 Cortex-A12
+         (all revs) erratum. Within rare timing constraints, executing a
+         DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
+         and Device/Strongly-Ordered loads and stores might cause deadlock
+ 
+ config ARM_ERRATA_852421
+       bool "ARM errata: A17: DMB ST might fail to create order between stores"
+       depends on CPU_V7
+       help
+         This option enables the workaround for the 852421 Cortex-A17
+         (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
+         execution of a DMB ST instruction might fail to properly order
+         stores from GroupA and stores from GroupB.
+ 
+ config ARM_ERRATA_852423
+       bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
+       depends on CPU_V7
+       help
+         This option enables the workaround for:
+         - Cortex-A17 852423: Execution of a sequence of instructions might
+           lead to either a data corruption or a CPU deadlock.  Not fixed in
+           any Cortex-A17 cores yet.
+         This is identical to Cortex-A12 erratum 852422.  It is a separate
+         config option from the A12 erratum due to the way errata are checked
+         for and handled.
+ 
  endmenu
  
  source "arch/arm/common/Kconfig"

diff --combined arch/arm/kernel/setup.c
index 261dae6f3fece20d58cecaaf5618ee9aa70b3fce,dd84f03dc2d40755576b1b1a97af908f32725489..85a0bcb1f7ca59704f47f10d8c4bb359fd655513
--- 1/arch/arm/kernel/setup.c
--- 2/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@@ -844,7 -844,7 +844,7 @@@ static void __init request_standard_res
        struct resource *res;
  
        kernel_code.start   = virt_to_phys(_text);
-       kernel_code.end     = virt_to_phys(_etext - 1);
+       kernel_code.end     = virt_to_phys(__init_begin - 1);
        kernel_data.start   = virt_to_phys(_sdata);
        kernel_data.end     = virt_to_phys(_end - 1);
  
@@@ -1064,7 -1064,6 +1064,7 @@@ void __init setup_arch(char **cmdline_p
        early_paging_init(mdesc);
  #endif
        setup_dma_zone(mdesc);
 +      xen_early_init();
        efi_init();
        sanity_check_meminfo();
        arm_memblock_init(mdesc);
@@@ -1081,6 -1080,7 +1081,6 @@@
  
        arm_dt_init_cpu_maps();
        psci_dt_init();
 -      xen_early_init();
  #ifdef CONFIG_SMP
        if (is_smp()) {
                if (!mdesc->smp_init || !mdesc->smp_init()) {