drm/i915/display: Add WA_14018221282

It was observed that the first write to DKL PHY DP Mode
register was not taking effect, hence rewrite this register.

v2: Rename function [Mitul]
v3: Rename function [Jani]
v4: Add check for display ver 13 [Matt]

Co-developed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241226060632.213790-1-nemesa.garg@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 05df8f98649124a80adb0111252cf45bbabef5f9..dc319f37b1be925ce1d88407e459481f73a582bc 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2120,10 +2120,21 @@ void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
        encoder->disable_clock(encoder);
 }
 
+static void
+tgl_dkl_phy_check_and_rewrite(struct drm_i915_private *dev_priv,
+                             enum tc_port tc_port, u32 ln0, u32 ln1)
+{
+       if (ln0 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)))
+               intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
+       if (ln1 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)))
+               intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
+}
+
 static void
 icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
                       const struct intel_crtc_state *crtc_state)
 {
+       struct intel_display *display = to_intel_display(crtc_state);
        struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
        enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base);
        u32 ln0, ln1, pin_assignment;
@@ -2201,6 +2212,10 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
        if (DISPLAY_VER(dev_priv) >= 12) {
                intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
                intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
+                /* WA_14018221282 */
+               if (IS_DISPLAY_VER(display, 12, 13))
+                       tgl_dkl_phy_check_and_rewrite(dev_priv, tc_port, ln0, ln1);
+
        } else {
                intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
                intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);