drm/amd/powerplay: add vclk/dclkSoftMin support for raven

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
index 4c7f430b36eba81ab13d76932bcabec2b5e50ff7..edc5fb6412d95be624dd3ef7903602c01b27c51d 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
@@ -265,6 +265,15 @@ static int rv_tf_set_clock_limit(struct pp_hwmgr *hwmgr, void *input,
                }
        } */
 
+       if (((hwmgr->uvd_arbiter.vclk_soft_min / 100) != rv_data->vclk_soft_min) ||
+           ((hwmgr->uvd_arbiter.dclk_soft_min / 100) != rv_data->dclk_soft_min)) {
+               rv_data->vclk_soft_min = hwmgr->uvd_arbiter.vclk_soft_min / 100;
+               rv_data->dclk_soft_min = hwmgr->uvd_arbiter.dclk_soft_min / 100;
+               smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+                       PPSMC_MSG_SetSoftMinVcn,
+                       (rv_data->vclk_soft_min << 16) | rv_data->vclk_soft_min);
+       }
+
        if((hwmgr->gfx_arbiter.sclk_hard_min != 0) &&
                ((hwmgr->gfx_arbiter.sclk_hard_min / 100) != rv_data->soc_actual_hard_min_freq)) {
                smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
index afb852295a1573d148fa6eaca387840f14033641..2472b50e54cfb67730176b47676c0ca1cc9f5163 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
@@ -280,6 +280,8 @@ struct rv_hwmgr {
 
        uint32_t                        f_actual_hard_min_freq;
        uint32_t                        fabric_actual_soft_min_freq;
+       uint32_t                        vclk_soft_min;
+       uint32_t                        dclk_soft_min;
        uint32_t                        gfx_actual_soft_min_freq;
 
        bool                           vcn_power_gated;

diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 47e57bd2c36f9b747c4a7632a1d488efcd13e40e..91b0105e82403c448cee8a6c303828f392e87eb8 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -128,6 +128,8 @@ struct phm_uvd_arbiter {
        uint32_t dclk;
        uint32_t vclk_ceiling;
        uint32_t dclk_ceiling;
+       uint32_t vclk_soft_min;
+       uint32_t dclk_soft_min;
 };
 
 struct phm_vce_arbiter {

diff --git a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
index e0e106f1b23a0de38a8222dc9d220afb04d549e2..901c960cfe21999787ea9d1b46dee00e5872c2da 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
@@ -66,7 +66,12 @@
 #define PPSMC_MSG_SetMinVddcrSocVoltage         0x22
 #define PPSMC_MSG_SetMinVideoFclkFreq           0x23
 #define PPSMC_MSG_SetMinDeepSleepDcefclk        0x24
-#define PPSMC_Message_Count                     0x25
+#define PPSMC_MSG_ForcePowerDownGfx             0x25
+#define PPSMC_MSG_SetPhyclkVoltageByFreq        0x26
+#define PPSMC_MSG_SetDppclkVoltageByFreq        0x27
+#define PPSMC_MSG_SetSoftMinVcn                 0x28
+#define PPSMC_Message_Count                     0x29
+
 
 typedef uint16_t PPSMC_Result;
 typedef int      PPSMC_Msg;