drm/i915/dpio: Use intel_de_rmw() for BXT DPIO latency optim setup

Replace the hand rolled intel_de_rmw() with the real thing.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240412175818.29217-6-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 3d1295da11064c9aaf2251443f43515a2caefca3..377963c0ed5faea750243a0b8c8170d7aeb944d7 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -613,19 +613,13 @@ void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
        bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
 
        for (lane = 0; lane < 4; lane++) {
-               u32 val = intel_de_read(dev_priv,
-                                       BXT_PORT_TX_DW14_LN(phy, ch, lane));
-
                /*
                 * Note that on CHV this flag is called UPAR, but has
                 * the same function.
                 */
-               val &= ~LATENCY_OPTIM;
-               if (lane_lat_optim_mask & BIT(lane))
-                       val |= LATENCY_OPTIM;
-
-               intel_de_write(dev_priv, BXT_PORT_TX_DW14_LN(phy, ch, lane),
-                              val);
+               intel_de_rmw(dev_priv, BXT_PORT_TX_DW14_LN(phy, ch, lane),
+                            LATENCY_OPTIM,
+                            lane_lat_optim_mask & BIT(lane) ? LATENCY_OPTIM : 0);
        }
 }