vxge: independent interrupt moderation
authorJon Mason <jon.mason@exar.com>
Fri, 10 Dec 2010 14:03:01 +0000 (14:03 +0000)
committerDavid S. Miller <davem@davemloft.net>
Sat, 11 Dec 2010 00:08:24 +0000 (16:08 -0800)
Configure the workload clock register and TIM register for independent
interrupt moderation based on the individual vpath utilization instead
of common link utilization.  This greatly improves latency.

Signed-off-by: Jon Mason <jon.mason@exar.com>
Signed-off-by: Ram Vepa <ram.vepa@exar.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/vxge/vxge-config.c

index 1169aa387caba0281cdbb4866683f272e2b43b1e..01c05f53e2f916df02a642843077a76cf7208a96 100644 (file)
@@ -4422,8 +4422,7 @@ __vxge_hw_vpath_tim_configure(struct __vxge_hw_device *hldev, u32 vp_id)
 
                if (config->tti.util_sel != VXGE_HW_USE_FLASH_DEFAULT) {
                        val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(0x3f);
-                       val64 |= VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(
-                                       config->tti.util_sel);
+                       val64 |= VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(vp_id);
                }
 
                if (config->tti.ltimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
@@ -4527,8 +4526,7 @@ __vxge_hw_vpath_tim_configure(struct __vxge_hw_device *hldev, u32 vp_id)
 
                if (config->rti.util_sel != VXGE_HW_USE_FLASH_DEFAULT) {
                        val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(0x3f);
-                       val64 |= VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(
-                                       config->rti.util_sel);
+                       val64 |= VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(vp_id);
                }
 
                if (config->rti.ltimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
@@ -4549,6 +4547,11 @@ __vxge_hw_vpath_tim_configure(struct __vxge_hw_device *hldev, u32 vp_id)
        writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_BMAP]);
        writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_BMAP]);
 
+       val64 = VXGE_HW_TIM_WRKLD_CLC_WRKLD_EVAL_PRD(150);
+       val64 |= VXGE_HW_TIM_WRKLD_CLC_WRKLD_EVAL_DIV(0);
+       val64 |= VXGE_HW_TIM_WRKLD_CLC_CNT_RX_TX(3);
+       writeq(val64, &vp_reg->tim_wrkld_clc);
+
        return status;
 }