net: mvpp2: check first level interrupt status registers

Check the first level interrupt status registers to determine how to
further process the port interrupt. We will need this to know whether
to invoke the link status processing and/or the PTP processing for
both XLG and GMAC.

Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
index a2f787c83756ce2cbf2f6b40100decc49691971d..273c46bbf927ed392d968f49e00c4ae770f10387 100644 (file)
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
@@ -461,6 +461,8 @@
 #define     MVPP22_CTRL4_DP_CLK_SEL            BIT(5)
 #define     MVPP22_CTRL4_SYNC_BYPASS_DIS       BIT(6)
 #define     MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE  BIT(7)
+#define MVPP22_GMAC_INT_SUM_STAT               0xa0
+#define            MVPP22_GMAC_INT_SUM_STAT_INTERNAL   BIT(1)
 #define MVPP22_GMAC_INT_SUM_MASK               0xa4
 #define     MVPP22_GMAC_INT_SUM_MASK_LINK_STAT BIT(1)
 
@@ -488,6 +490,8 @@
 #define     MVPP22_XLG_CTRL3_MACMODESELECT_MASK        (7 << 13)
 #define     MVPP22_XLG_CTRL3_MACMODESELECT_GMAC        (0 << 13)
 #define     MVPP22_XLG_CTRL3_MACMODESELECT_10G (1 << 13)
+#define MVPP22_XLG_EXT_INT_STAT                        0x158
+#define     MVPP22_XLG_EXT_INT_STAT_XLG                BIT(1)
 #define MVPP22_XLG_EXT_INT_MASK                        0x15c
 #define     MVPP22_XLG_EXT_INT_MASK_XLG                BIT(1)
 #define     MVPP22_XLG_EXT_INT_MASK_GIG                BIT(2)

diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
index d85ba26ba886a197a714d77cf194f332baca0425..8a1f03f9d5d7437fbc44149c5e7a922eb93c5e64 100644 (file)
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
@@ -3039,14 +3039,23 @@ static void mvpp2_isr_handle_gmac_internal(struct mvpp2_port *port)
 static irqreturn_t mvpp2_port_isr(int irq, void *dev_id)
 {
        struct mvpp2_port *port = (struct mvpp2_port *)dev_id;
+       u32 val;
 
        mvpp22_gop_mask_irq(port);
 
        if (mvpp2_port_supports_xlg(port) &&
            mvpp2_is_xlg(port->phy_interface)) {
-               mvpp2_isr_handle_xlg(port);
+               /* Check the external status register */
+               val = readl(port->base + MVPP22_XLG_EXT_INT_STAT);
+               if (val & MVPP22_XLG_EXT_INT_STAT_XLG)
+                       mvpp2_isr_handle_xlg(port);
        } else {
-               mvpp2_isr_handle_gmac_internal(port);
+               /* If it's not the XLG, we must be using the GMAC.
+                * Check the summary status.
+                */
+               val = readl(port->base + MVPP22_GMAC_INT_SUM_STAT);
+               if (val & MVPP22_GMAC_INT_SUM_STAT_INTERNAL)
+                       mvpp2_isr_handle_gmac_internal(port);
        }
 
        mvpp22_gop_unmask_irq(port);