arm64: dts: mediatek: add afe support for mt8365 SoC

Add audio front end support of MT8365 SoC.
Update the file header.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Link: https://lore.kernel.org/r/20240226-audio-i350-v8-4-e80a57d026ce@baylibre.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
index eb449bfa88030c5a9757cb9c4aab8cee751e9dbc..9c91fe8ea0f969770a611f90b593683f93ff3e22 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
@@ -2,9 +2,11 @@
 /*
  * (C) 2018 MediaTek Inc.
  * Copyright (C) 2022 BayLibre SAS
- * Fabien Parent <fparent@baylibre.com>
- * Bernhard Rosenkränzer <bero@baylibre.com>
+ * Authors: Fabien Parent <fparent@baylibre.com>
+ *         Bernhard Rosenkränzer <bero@baylibre.com>
+ *         Alexandre Mergnat <amergnat@baylibre.com>
  */
+
 #include <dt-bindings/clock/mediatek,mt8365-clk.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
@@ -812,6 +814,43 @@
                        reg = <0 0x19020000 0 0x1000>;
                        #clock-cells = <1>;
                };
+
+               afe: audio-controller@11220000 {
+                       compatible = "mediatek,mt8365-afe-pcm";
+                       reg = <0 0x11220000 0 0x1000>;
+                       #sound-dai-cells = <0>;
+                       clocks = <&clk26m>,
+                                <&topckgen CLK_TOP_AUDIO_SEL>,
+                                <&topckgen CLK_TOP_AUD_I2S0_M>,
+                                <&topckgen CLK_TOP_AUD_I2S1_M>,
+                                <&topckgen CLK_TOP_AUD_I2S2_M>,
+                                <&topckgen CLK_TOP_AUD_I2S3_M>,
+                                <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
+                                <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
+                                <&topckgen CLK_TOP_AUD_1_SEL>,
+                                <&topckgen CLK_TOP_AUD_2_SEL>,
+                                <&topckgen CLK_TOP_APLL_I2S0_SEL>,
+                                <&topckgen CLK_TOP_APLL_I2S1_SEL>,
+                                <&topckgen CLK_TOP_APLL_I2S2_SEL>,
+                                <&topckgen CLK_TOP_APLL_I2S3_SEL>;
+                       clock-names = "top_clk26m_clk",
+                                     "top_audio_sel",
+                                     "audio_i2s0_m",
+                                     "audio_i2s1_m",
+                                     "audio_i2s2_m",
+                                     "audio_i2s3_m",
+                                     "engen1",
+                                     "engen2",
+                                     "aud1",
+                                     "aud2",
+                                     "i2s0_m_sel",
+                                     "i2s1_m_sel",
+                                     "i2s2_m_sel",
+                                     "i2s3_m_sel";
+                       interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
+                       power-domains = <&spm MT8365_POWER_DOMAIN_AUDIO>;
+                       status = "disabled";
+               };
        };
 
        timer {