drm/i915: Clean up DVO pipe select bits

Parametrize the DVO pipe select bits.

For consistency with the new way of doing things, let's read out the
pipe select bits even when the port is disable, even though we don't
need that behaviour for asserts in this case.

v2: Order the defines shift,mask,value (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180514172423.9302-5-ville.syrjala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dae213d4c13ab170d84718ec312836ef9bfab6dc..196a0eb79272535559390fdcc1daf30830e7c61e 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4357,7 +4357,9 @@ enum {
 #define _DVOC                  0x61160
 #define DVOC                   _MMIO(_DVOC)
 #define   DVO_ENABLE                   (1 << 31)
-#define   DVO_PIPE_B_SELECT            (1 << 30)
+#define   DVO_PIPE_SEL_SHIFT           30
+#define   DVO_PIPE_SEL_MASK            (1 << 30)
+#define   DVO_PIPE_SEL(pipe)           ((pipe) << 30)
 #define   DVO_PIPE_STALL_UNUSED                (0 << 28)
 #define   DVO_PIPE_STALL               (1 << 28)
 #define   DVO_PIPE_STALL_TV            (2 << 28)

diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index eb0c559b27156c0a49e31d342e865e7e88d1ea15..a86f0398570f634958c653bb9a89aff78e5dfab2 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -137,19 +137,15 @@ static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector)
 static bool intel_dvo_get_hw_state(struct intel_encoder *encoder,
                                   enum pipe *pipe)
 {
-       struct drm_device *dev = encoder->base.dev;
-       struct drm_i915_private *dev_priv = to_i915(dev);
+       struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
        struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
        u32 tmp;
 
        tmp = I915_READ(intel_dvo->dev.dvo_reg);
 
-       if (!(tmp & DVO_ENABLE))
-               return false;
-
-       *pipe = PORT_TO_PIPE(tmp);
+       *pipe = (tmp & DVO_PIPE_SEL_MASK) >> DVO_PIPE_SEL_SHIFT;
 
-       return true;
+       return tmp & DVO_ENABLE;
 }
 
 static void intel_dvo_get_config(struct intel_encoder *encoder,
@@ -276,8 +272,7 @@ static void intel_dvo_pre_enable(struct intel_encoder *encoder,
        dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE |
                   DVO_BLANK_ACTIVE_HIGH;
 
-       if (pipe == 1)
-               dvo_val |= DVO_PIPE_B_SELECT;
+       dvo_val |= DVO_PIPE_SEL(pipe);
        dvo_val |= DVO_PIPE_STALL;
        if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
                dvo_val |= DVO_HSYNC_ACTIVE_HIGH;