drm/amd/display: pass calculated dram_speed_mts to dml2

[why]
currently dml2 is using a hard coded 16 to convert memclk to dram_speed_mts.
for apu, this depends on wck_ratio.

change to pass the already calculated dram_speed_mts from fpu to dml2.

v2: use existing calculation of dram_speed_mts for now to avoid regression

Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
index 47d785204f29cb5a23dd3e74e8c8a7fcab3759ab..e8efffcc69a162f6d8548ee3fe0e251d2822bdfb 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
@@ -367,6 +367,8 @@ void dcn35_update_bw_bounding_box_fpu(struct dc *dc,
                                clock_limits[i].socclk_mhz;
                        dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz =
                                clk_table->entries[i].memclk_mhz * clk_table->entries[i].wck_ratio;
+
+                       dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dram_speed_mts = clock_limits[i].dram_speed_mts;
                        dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz =
                                clock_limits[i].dtbclk_mhz;
                        dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels =

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
index d9e63c4fdd95cd5a64ce20d4ace14a19c01d2f05..17d0b4923b0cc42835475b3889a4fa9d43c93b42 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
@@ -401,6 +401,7 @@ void dcn351_update_bw_bounding_box_fpu(struct dc *dc,
                                clock_limits[i].socclk_mhz;
                        dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz =
                                clk_table->entries[i].memclk_mhz * clk_table->entries[i].wck_ratio;
+                       dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dram_speed_mts = clock_limits[i].dram_speed_mts;
                        dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz =
                                clock_limits[i].dtbclk_mhz;
                        dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels =

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h
index 0f944fcfd5a5bba0a010df53634fae350378bc17..785226945699dd57953ba381bfec0cd892fb54ea 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h
@@ -159,6 +159,7 @@ struct dml2_clks_table_entry {
        unsigned int dtbclk_mhz;
        unsigned int dispclk_mhz;
        unsigned int dppclk_mhz;
+       unsigned int dram_speed_mts; /*which is based on wck_ratio*/
 };
 
 struct dml2_clks_num_entries {