iio: dac: ad5764: Fix alignment for DMA safety

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Update the comment to include 'may'.

Fixes: 68b14d7ea956 ("staging:iio:dac: Add AD5764 driver")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-53-jic23@kernel.org

diff --git a/drivers/iio/dac/ad5764.c b/drivers/iio/dac/ad5764.c
index d235a8047ba0c62a3ac72e5faea3a1d55c9b5b9e..26c049d5b73a5cf9044a4e82b9908dd9c9b68465 100644 (file)
--- a/drivers/iio/dac/ad5764.c
+++ b/drivers/iio/dac/ad5764.c
@@ -56,13 +56,13 @@ struct ad5764_state {
        struct mutex                    lock;
 
        /*
-        * DMA (thus cache coherency maintenance) requires the
+        * DMA (thus cache coherency maintenance) may require the
         * transfer buffers to live in their own cache lines.
         */
        union {
                __be32 d32;
                u8 d8[4];
-       } data[2] ____cacheline_aligned;
+       } data[2] __aligned(IIO_DMA_MINALIGN);
 };
 
 enum ad5764_type {