bool debug_largebar;
bool debug_disable_soft_recovery;
bool debug_use_vram_fw_buf;
+ bool debug_enable_ras_aca;
};
static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev,
bool amdgpu_aca_is_enabled(struct amdgpu_device *adev)
{
- return adev->aca.is_enabled;
+ return (adev->aca.is_enabled ||
+ adev->debug_enable_ras_aca);
}
int amdgpu_aca_init(struct amdgpu_device *adev)
AMDGPU_DEBUG_LARGEBAR = BIT(1),
AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2),
AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3),
+ AMDGPU_DEBUG_ENABLE_RAS_ACA = BIT(4),
};
unsigned int amdgpu_vram_limit = UINT_MAX;
pr_info("debug: place fw in vram for frontdoor loading\n");
adev->debug_use_vram_fw_buf = true;
}
+
+ if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_RAS_ACA) {
+ pr_info("debug: enable RAS ACA\n");
+ adev->debug_enable_ras_aca = true;
+ }
}
static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags)