drm/i915/dmc: Add PIPEDMC_EVT_CTL register definition

To implement workaround for underrun on idle PSR HW issue (Wa_16025596647)
we need PIPEDMC_EVT_CTL_4 register. Add PIPEDMC_EVT_CTL_4 register
definitions.

Bspec: 67576

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://lore.kernel.org/r/20250414100508.1208774-4-jouni.hogander@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
index 1bf446f96a10c4eb3096593c1e6b4dd9e0a2e50b..2f1e3cb1a24772b6f91118d2630836c530592393 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
@@ -21,6 +21,12 @@
 #define MTL_PIPEDMC_CONTROL            _MMIO(0x45250)
 #define  PIPEDMC_ENABLE_MTL(pipe)      REG_BIT(((pipe) - PIPE_A) * 4)
 
+#define _MTL_PIPEDMC_EVT_CTL_4_A       0x5f044
+#define _MTL_PIPEDMC_EVT_CTL_4_B       0x5f444
+#define MTL_PIPEDMC_EVT_CTL_4(pipe)    _MMIO_PIPE(pipe,                \
+                                                  _MTL_PIPEDMC_EVT_CTL_4_A, \
+                                                  _MTL_PIPEDMC_EVT_CTL_4_B)
+
 #define _ADLP_PIPEDMC_REG_MMIO_BASE_A  0x5f000
 #define _TGL_PIPEDMC_REG_MMIO_BASE_A   0x92000