arm64: dts: s32g: add I2C[0..2] support for s32g2 and s32g3

Add I2C[0..2] for S32G2 and S32G3 SoCs.

Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 7be430b78c83d3feba4b33b9fb7c744bd55b37ba..beae4d5cf54e4cc5479dff3620c3817d630b3568 100644 (file)
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -333,6 +333,39 @@
                        status = "disabled";
                };
 
+               i2c0: i2c@401e4000 {
+                       compatible = "nxp,s32g2-i2c";
+                       reg = <0x401e4000 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clks 40>;
+                       clock-names = "ipg";
+                       status = "disabled";
+               };
+
+               i2c1: i2c@401e8000 {
+                       compatible = "nxp,s32g2-i2c";
+                       reg = <0x401e8000 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clks 40>;
+                       clock-names = "ipg";
+                       status = "disabled";
+               };
+
+               i2c2: i2c@401ec000 {
+                       compatible = "nxp,s32g2-i2c";
+                       reg = <0x401ec000 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clks 40>;
+                       clock-names = "ipg";
+                       status = "disabled";
+               };
+
                uart2: serial@402bc000 {
                        compatible = "nxp,s32g2-linflexuart",
                                     "fsl,s32v234-linflexuart";
@@ -341,6 +374,28 @@
                        status = "disabled";
                };
 
+               i2c3: i2c@402d8000 {
+                       compatible = "nxp,s32g2-i2c";
+                       reg = <0x402d8000 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clks 40>;
+                       clock-names = "ipg";
+                       status = "disabled";
+               };
+
+               i2c4: i2c@402dc000 {
+                       compatible = "nxp,s32g2-i2c";
+                       reg = <0x402dc000 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clks 40>;
+                       clock-names = "ipg";
+                       status = "disabled";
+               };
+
                usdhc0: mmc@402f0000 {
                        compatible = "nxp,s32g2-usdhc";
                        reg = <0x402f0000 0x1000>;

diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
index 6c572ffe37caf8d4842e5606ea45682a634c3906..79b38cd8b142145e27cdc50e099b0b6a6c96e9ad 100644 (file)
--- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
@@ -390,6 +390,42 @@
                        status = "disabled";
                };
 
+               i2c0: i2c@401e4000 {
+                       compatible = "nxp,s32g3-i2c",
+                                    "nxp,s32g2-i2c";
+                       reg = <0x401e4000 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clks 40>;
+                       clock-names = "ipg";
+                       status = "disabled";
+               };
+
+               i2c1: i2c@401e8000 {
+                       compatible = "nxp,s32g3-i2c",
+                                    "nxp,s32g2-i2c";
+                       reg = <0x401e8000 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clks 40>;
+                       clock-names = "ipg";
+                       status = "disabled";
+               };
+
+               i2c2: i2c@401ec000 {
+                       compatible = "nxp,s32g3-i2c",
+                                    "nxp,s32g2-i2c";
+                       reg = <0x401ec000 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clks 40>;
+                       clock-names = "ipg";
+                       status = "disabled";
+               };
+
                uart2: serial@402bc000 {
                        compatible = "nxp,s32g3-linflexuart",
                                     "fsl,s32v234-linflexuart";
@@ -398,6 +434,30 @@
                        status = "disabled";
                };
 
+               i2c3: i2c@402d8000 {
+                       compatible = "nxp,s32g3-i2c",
+                                    "nxp,s32g2-i2c";
+                       reg = <0x402d8000 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clks 40>;
+                       clock-names = "ipg";
+                       status = "disabled";
+               };
+
+               i2c4: i2c@402dc000 {
+                       compatible = "nxp,s32g3-i2c",
+                                    "nxp,s32g2-i2c";
+                       reg = <0x402dc000 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clks 40>;
+                       clock-names = "ipg";
+                       status = "disabled";
+               };
+
                usdhc0: mmc@402f0000 {
                        compatible = "nxp,s32g3-usdhc",
                                     "nxp,s32g2-usdhc";