arm64: dts: apple: s8001: Add cpufreq nodes

Add cpufreq nodes for Apple A9X SoC.

Signed-off-by: Nick Chan <towinchenmi@gmail.com>
Reviewed-by: Neal Gompa <neal@gompa.dev>
Signed-off-by: Sven Peter <sven@svenpeter.dev>

diff --git a/arch/arm64/boot/dts/apple/s8001.dtsi b/arch/arm64/boot/dts/apple/s8001.dtsi
index 3963c6d8ca5efc2913dc80b053e0584f0e75b7ce..d56d49c048bbf55e5f2edf40f6fd1fcff6342a9f 100644 (file)
--- a/arch/arm64/boot/dts/apple/s8001.dtsi
+++ b/arch/arm64/boot/dts/apple/s8001.dtsi
@@ -32,6 +32,8 @@
                        compatible = "apple,twister";
                        reg = <0x0 0x0>;
                        cpu-release-addr = <0 0>; /* To be filled in by loader */
+                       operating-points-v2 = <&twister_opp>;
+                       performance-domains = <&cpufreq>;
                        enable-method = "spin-table";
                        device_type = "cpu";
                };
@@ -40,11 +42,62 @@
                        compatible = "apple,twister";
                        reg = <0x0 0x1>;
                        cpu-release-addr = <0 0>; /* To be filled in by loader */
+                       operating-points-v2 = <&twister_opp>;
+                       performance-domains = <&cpufreq>;
                        enable-method = "spin-table";
                        device_type = "cpu";
                };
        };
 
+       twister_opp: opp-table {
+               compatible = "operating-points-v2";
+
+               opp01 {
+                       opp-hz = /bits/ 64 <300000000>;
+                       opp-level = <1>;
+                       clock-latency-ns = <800>;
+               };
+               opp02 {
+                       opp-hz = /bits/ 64 <396000000>;
+                       opp-level = <2>;
+                       clock-latency-ns = <53000>;
+               };
+               opp03 {
+                       opp-hz = /bits/ 64 <792000000>;
+                       opp-level = <3>;
+                       clock-latency-ns = <18000>;
+               };
+               opp04 {
+                       opp-hz = /bits/ 64 <1080000000>;
+                       opp-level = <4>;
+                       clock-latency-ns = <21000>;
+               };
+               opp05 {
+                       opp-hz = /bits/ 64 <1440000000>;
+                       opp-level = <5>;
+                       clock-latency-ns = <25000>;
+               };
+               opp06 {
+                       opp-hz = /bits/ 64 <1800000000>;
+                       opp-level = <6>;
+                       clock-latency-ns = <33000>;
+               };
+               opp07 {
+                       opp-hz = /bits/ 64 <2160000000>;
+                       opp-level = <7>;
+                       clock-latency-ns = <45000>;
+               };
+#if 0
+               /* Not available until CPU deep sleep is implemented */
+               opp08 {
+                       opp-hz = /bits/ 64 <2160000000>;
+                       opp-level = <8>;
+                       clock-latency-ns = <45000>;
+                       turbo-mode;
+               };
+#endif
+       };
+
        soc {
                compatible = "simple-bus";
                #address-cells = <2>;
@@ -52,6 +105,12 @@
                nonposted-mmio;
                ranges;
 
+               cpufreq: performance-controller@202220000 {
+                       compatible = "apple,s8000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
+                       reg = <0x2 0x02220000 0 0x1000>;
+                       #performance-domain-cells = <0>;
+               };
+
                serial0: serial@20a0c0000 {
                        compatible = "apple,s5l-uart";
                        reg = <0x2 0x0a0c0000 0x0 0x4000>;