uint32_t u32All;
};
+union dpia_debug_options {
+ struct {
+ uint32_t disable_dpia:1;
+ uint32_t reserved:31;
+ } bits;
+ uint32_t raw;
+};
+
struct dc_debug_data {
uint32_t ltFailCount;
uint32_t i2cErrorCount;
#if defined(CONFIG_DRM_AMD_DC_DCN)
bool disable_z10;
bool enable_sw_cntl_psr;
+ union dpia_debug_options dpia_debug;
#endif
};
}
if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&
- dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
+ dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&
+ !dc->debug.dpia_debug.bits.disable_dpia) {
/* YELLOW CARP B0 has 4 DPIA's */
pool->base.usb4_dpia_count = 4;
}
bool load_inst_const;
bool skip_panel_power_sequence;
bool disable_z10;
+ bool disable_dpia;
};
/**
uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */
uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */
uint32_t z10_disable: 1; /**< 1 to disable z10 */
- uint32_t reserved2: 1; /**< reserved for an unreleased feature */
- uint32_t reserved_unreleased1: 1; /**< reserved for an unreleased feature */
+ uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */
uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */
uint32_t reserved_unreleased2: 1; /**< reserved for an unreleased feature */
uint32_t reserved : 22; /**< reserved */
union dmub_fw_boot_options boot_options = {0};
boot_options.bits.z10_disable = params->disable_z10;
+ boot_options.bits.enable_dpia = params->disable_dpia ? 0 : 1;
REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
}