drm/amdgpu/mes: initialize/finalize common mes structure v2

Initialize/finalize common mes structure.

v2: add mutex_init for adev->mes.mutex

Cc: Le Ma <le.ma@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index 1c591cb45fd970e79f40f6fef8888cbe8926a9dc..90c400564540f1e39bed50bbc4db4e14d810369a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -131,3 +131,75 @@ static int amdgpu_mes_doorbell_init(struct amdgpu_device *adev)
        DRM_INFO("max_doorbell_slices=%ld\n", doorbell_process_limit);
        return 0;
 }
+
+int amdgpu_mes_init(struct amdgpu_device *adev)
+{
+       int i, r;
+
+       adev->mes.adev = adev;
+
+       idr_init(&adev->mes.pasid_idr);
+       idr_init(&adev->mes.gang_id_idr);
+       idr_init(&adev->mes.queue_id_idr);
+       ida_init(&adev->mes.doorbell_ida);
+       spin_lock_init(&adev->mes.queue_id_lock);
+       mutex_init(&adev->mes.mutex);
+
+       adev->mes.total_max_queue = AMDGPU_FENCE_MES_QUEUE_ID_MASK;
+       adev->mes.vmid_mask_mmhub = 0xffffff00;
+       adev->mes.vmid_mask_gfxhub = 0xffffff00;
+
+       for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) {
+               /* use only 1st MEC pipes */
+               if (i >= 4)
+                       continue;
+               adev->mes.compute_hqd_mask[i] = 0xc;
+       }
+
+       for (i = 0; i < AMDGPU_MES_MAX_GFX_PIPES; i++)
+               adev->mes.gfx_hqd_mask[i] = i ? 0 : 0xfffffffe;
+
+       for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++)
+               adev->mes.sdma_hqd_mask[i] = i ? 0 : 0x3fc;
+
+       for (i = 0; i < AMDGPU_MES_PRIORITY_NUM_LEVELS; i++)
+               adev->mes.agreegated_doorbells[i] = 0xffffffff;
+
+       r = amdgpu_device_wb_get(adev, &adev->mes.sch_ctx_offs);
+       if (r) {
+               dev_err(adev->dev,
+                       "(%d) ring trail_fence_offs wb alloc failed\n", r);
+               goto error_ids;
+       }
+       adev->mes.sch_ctx_gpu_addr =
+               adev->wb.gpu_addr + (adev->mes.sch_ctx_offs * 4);
+       adev->mes.sch_ctx_ptr =
+               (uint64_t *)&adev->wb.wb[adev->mes.sch_ctx_offs];
+
+       r = amdgpu_mes_doorbell_init(adev);
+       if (r)
+               goto error;
+
+       return 0;
+
+error:
+       amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs);
+error_ids:
+       idr_destroy(&adev->mes.pasid_idr);
+       idr_destroy(&adev->mes.gang_id_idr);
+       idr_destroy(&adev->mes.queue_id_idr);
+       ida_destroy(&adev->mes.doorbell_ida);
+       mutex_destroy(&adev->mes.mutex);
+       return r;
+}
+
+void amdgpu_mes_fini(struct amdgpu_device *adev)
+{
+       amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs);
+
+       idr_destroy(&adev->mes.pasid_idr);
+       idr_destroy(&adev->mes.gang_id_idr);
+       idr_destroy(&adev->mes.queue_id_idr);
+       ida_destroy(&adev->mes.doorbell_ida);
+       mutex_destroy(&adev->mes.mutex);
+}

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
index 35a6bb2b4be89e9be151e13b20921d45eb89ad08..45c0a246b618836abb476afae4de93dc1b64fa9a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
@@ -208,6 +208,10 @@ struct amdgpu_mes_funcs {
                           struct mes_resume_gang_input *input);
 };
 
+
 #define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev))
 
+int amdgpu_mes_init(struct amdgpu_device *adev);
+void amdgpu_mes_fini(struct amdgpu_device *adev);
+
 #endif /* __AMDGPU_MES_H__ */