Reapply: drm/amdgpu: Use generic hdp flush function

Except HDP v5.2 all use a common logic for HDP flush. Use a generic
function. HDP v5.2 forces NO_KIQ logic, revisit it later.

Reapply after fixing up an HDP regression.

v2: merge the fix (Alex)

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> (v1)
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c
index b6cf801939aa58ffd11893d5be642ee4df622d22..6e02fb9ac2f67d842ab514d66c9c68cff62b3c2d 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c
@@ -22,6 +22,7 @@
  */
 #include "amdgpu.h"
 #include "amdgpu_ras.h"
+#include <uapi/linux/kfd_ioctl.h>
 
 int amdgpu_hdp_ras_sw_init(struct amdgpu_device *adev)
 {
@@ -46,3 +47,22 @@ int amdgpu_hdp_ras_sw_init(struct amdgpu_device *adev)
        /* hdp ras follows amdgpu_ras_block_late_init_default for late init */
        return 0;
 }
+
+void amdgpu_hdp_generic_flush(struct amdgpu_device *adev,
+                             struct amdgpu_ring *ring)
+{
+       if (!ring || !ring->funcs->emit_wreg) {
+               WREG32((adev->rmmio_remap.reg_offset +
+                       KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >>
+                              2,
+                      0);
+               if (adev->nbio.funcs->get_memsize)
+                       adev->nbio.funcs->get_memsize(adev);
+       } else {
+               amdgpu_ring_emit_wreg(ring,
+                                     (adev->rmmio_remap.reg_offset +
+                                      KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >>
+                                             2,
+                                     0);
+       }
+}

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h
index 7b8a6152dc8d9edac9e932b420b01f778fbd0a6f..4cfd932b7e91edf8633939cb2f8d1af7e529329c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h
@@ -44,4 +44,6 @@ struct amdgpu_hdp {
 };
 
 int amdgpu_hdp_ras_sw_init(struct amdgpu_device *adev);
+void amdgpu_hdp_generic_flush(struct amdgpu_device *adev,
+                             struct amdgpu_ring *ring);
 #endif /* __AMDGPU_HDP_H__ */

diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
index cbbeadeb53f72dbae6434f46d70da8922b4df1c9..e6c0d86d34865bc0ebf21a01c2474ff752f90f08 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
@@ -36,22 +36,6 @@
 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK     0x00020000L
 #define mmHDP_MEM_POWER_CTRL_BASE_IDX   0
 
-static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev,
-                               struct amdgpu_ring *ring)
-{
-       if (!ring || !ring->funcs->emit_wreg) {
-               WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
-               /* We just need to read back a register to post the write.
-                * Reading back the remapped register causes problems on
-                * some platforms so just read back the memory size register.
-                */
-               if (adev->nbio.funcs->get_memsize)
-                       adev->nbio.funcs->get_memsize(adev);
-       } else {
-               amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
-       }
-}
-
 static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev,
                                    struct amdgpu_ring *ring)
 {
@@ -185,7 +169,7 @@ struct amdgpu_hdp_ras hdp_v4_0_ras = {
 };
 
 const struct amdgpu_hdp_funcs hdp_v4_0_funcs = {
-       .flush_hdp = hdp_v4_0_flush_hdp,
+       .flush_hdp = amdgpu_hdp_generic_flush,
        .invalidate_hdp = hdp_v4_0_invalidate_hdp,
        .update_clock_gating = hdp_v4_0_update_clock_gating,
        .get_clock_gating_state = hdp_v4_0_get_clockgating_state,

diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c
index 086a647308df07ac027d34c3dbf496357d98386f..8bc001dc9f631a19b2485d5be498031ae76c2a95 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c
@@ -27,22 +27,6 @@
 #include "hdp/hdp_5_0_0_sh_mask.h"
 #include <uapi/linux/kfd_ioctl.h>
 
-static void hdp_v5_0_flush_hdp(struct amdgpu_device *adev,
-                               struct amdgpu_ring *ring)
-{
-       if (!ring || !ring->funcs->emit_wreg) {
-               WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
-               /* We just need to read back a register to post the write.
-                * Reading back the remapped register causes problems on
-                * some platforms so just read back the memory size register.
-                */
-               if (adev->nbio.funcs->get_memsize)
-                       adev->nbio.funcs->get_memsize(adev);
-       } else {
-               amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
-       }
-}
-
 static void hdp_v5_0_invalidate_hdp(struct amdgpu_device *adev,
                                    struct amdgpu_ring *ring)
 {
@@ -222,7 +206,7 @@ static void hdp_v5_0_init_registers(struct amdgpu_device *adev)
 }
 
 const struct amdgpu_hdp_funcs hdp_v5_0_funcs = {
-       .flush_hdp = hdp_v5_0_flush_hdp,
+       .flush_hdp = amdgpu_hdp_generic_flush,
        .invalidate_hdp = hdp_v5_0_invalidate_hdp,
        .update_clock_gating = hdp_v5_0_update_clock_gating,
        .get_clock_gating_state = hdp_v5_0_get_clockgating_state,

diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c
index 6ccd31c8bc69289239abf83fe7b81db9423fda06..ec20daf4272c5d5951cf41ac9ccd0b93fc93593e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c
@@ -30,22 +30,6 @@
 #define regHDP_CLK_CNTL_V6_1   0xd5
 #define regHDP_CLK_CNTL_V6_1_BASE_IDX 0
 
-static void hdp_v6_0_flush_hdp(struct amdgpu_device *adev,
-                               struct amdgpu_ring *ring)
-{
-       if (!ring || !ring->funcs->emit_wreg) {
-               WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
-               /* We just need to read back a register to post the write.
-                * Reading back the remapped register causes problems on
-                * some platforms so just read back the memory size register.
-                */
-               if (adev->nbio.funcs->get_memsize)
-                       adev->nbio.funcs->get_memsize(adev);
-       } else {
-               amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
-       }
-}
-
 static void hdp_v6_0_update_clock_gating(struct amdgpu_device *adev,
                                         bool enable)
 {
@@ -154,7 +138,7 @@ static void hdp_v6_0_get_clockgating_state(struct amdgpu_device *adev,
 }
 
 const struct amdgpu_hdp_funcs hdp_v6_0_funcs = {
-       .flush_hdp = hdp_v6_0_flush_hdp,
+       .flush_hdp = amdgpu_hdp_generic_flush,
        .update_clock_gating = hdp_v6_0_update_clock_gating,
        .get_clock_gating_state = hdp_v6_0_get_clockgating_state,
 };

diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c
index 2c9239a22f39869005b19a3030c6bb8bbee25d13..ed1debc035073a3f7348c1f21c2e89611d90516c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c
@@ -27,22 +27,6 @@
 #include "hdp/hdp_7_0_0_sh_mask.h"
 #include <uapi/linux/kfd_ioctl.h>
 
-static void hdp_v7_0_flush_hdp(struct amdgpu_device *adev,
-                               struct amdgpu_ring *ring)
-{
-       if (!ring || !ring->funcs->emit_wreg) {
-               WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
-               /* We just need to read back a register to post the write.
-                * Reading back the remapped register causes problems on
-                * some platforms so just read back the memory size register.
-                */
-               if (adev->nbio.funcs->get_memsize)
-                       adev->nbio.funcs->get_memsize(adev);
-       } else {
-               amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
-       }
-}
-
 static void hdp_v7_0_update_clock_gating(struct amdgpu_device *adev,
                                         bool enable)
 {
@@ -142,7 +126,7 @@ static void hdp_v7_0_get_clockgating_state(struct amdgpu_device *adev,
 }
 
 const struct amdgpu_hdp_funcs hdp_v7_0_funcs = {
-       .flush_hdp = hdp_v7_0_flush_hdp,
+       .flush_hdp = amdgpu_hdp_generic_flush,
        .update_clock_gating = hdp_v7_0_update_clock_gating,
        .get_clock_gating_state = hdp_v7_0_get_clockgating_state,
 };