perf vendor events arm64: Move Yitian 710 DDR PMU into T-Head directory

The Yitian 710 is not a Freescale/NXP design and thus should
be located in a separate T-Head vendor directory.

Reviewed-by: Jing Zhang <renyu.zj@linux.alibaba.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@linux.dev>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Shuai Xue <xueshuai@linux.alibaba.com>
Cc: Will Deacon <will@kernel.org>
Cc: kernel@pengutronix.de
Cc: linux-arm-kernel@lists.infradead.org
Cc: patchwork-lst@pengutronix.de
Link: https://lore.kernel.org/r/20240701175735.485655-1-l.stach@pengutronix.de
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

diff --git a/tools/perf/pmu-events/arch/arm64/freescale/yitian710/sys/ali_drw.json b/tools/perf/pmu-events/arch/arm64/freescale/yitian710/sys/ali_drw.json
deleted file mode 100644 (file)
index e21c469..0000000
--- a/tools/perf/pmu-events/arch/arm64/freescale/yitian710/sys/ali_drw.json
+++ /dev/null
@@ -1,373 +0,0 @@
-[
-       {
-               "BriefDescription": "A Write or Read Op at HIF interface. The unit is 64B.",
-               "ConfigCode": "0x0",
-               "EventName": "hif_rd_or_wr",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "A Write Op at HIF interface. The unit is 64B.",
-               "ConfigCode": "0x1",
-               "EventName": "hif_wr",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "A Read Op at HIF interface. The unit is 64B.",
-               "ConfigCode": "0x2",
-               "EventName": "hif_rd",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "A Read-Modify-Write Op at HIF interface. The unit is 64B.",
-               "ConfigCode": "0x3",
-               "EventName": "hif_rmw",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "A high priority Read at HIF interface. The unit is 64B.",
-               "ConfigCode": "0x4",
-               "EventName": "hif_hi_pri_rd",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "A write data cycle at DFI interface (to DRAM).",
-               "ConfigCode": "0x7",
-               "EventName": "dfi_wr_data_cycles",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "A read data cycle at DFI interface (to DRAM).",
-               "ConfigCode": "0x8",
-               "EventName": "dfi_rd_data_cycles",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "A high priority read becomes critical.",
-               "ConfigCode": "0x9",
-               "EventName": "hpr_xact_when_critical",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "A low priority read becomes critical.",
-               "ConfigCode": "0xA",
-               "EventName": "lpr_xact_when_critical",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "A write becomes critical.",
-               "ConfigCode": "0xB",
-               "EventName": "wr_xact_when_critical",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "An Activate(ACT) command to DRAM.",
-               "ConfigCode": "0xC",
-               "EventName": "op_is_activate",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "A Read or Write CAS command to DRAM.",
-               "ConfigCode": "0xD",
-               "EventName": "op_is_rd_or_wr",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "An Activate(ACT) command for read to DRAM.",
-               "ConfigCode": "0xE",
-               "EventName": "op_is_rd_activate",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "A Read CAS command to DRAM.",
-               "ConfigCode": "0xF",
-               "EventName": "op_is_rd",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "A Write CAS command to DRAM.",
-               "ConfigCode": "0x10",
-               "EventName": "op_is_wr",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "A Masked Write command to DRAM.",
-               "ConfigCode": "0x11",
-               "EventName": "op_is_mwr",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "A Precharge(PRE) command to DRAM.",
-               "ConfigCode": "0x12",
-               "EventName": "op_is_precharge",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "A Precharge(PRE) required by read or write.",
-               "ConfigCode": "0x13",
-               "EventName": "precharge_for_rdwr",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "A Precharge(PRE) required by other conditions.",
-               "ConfigCode": "0x14",
-               "EventName": "precharge_for_other",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "A read-write turnaround.",
-               "ConfigCode": "0x15",
-               "EventName": "rdwr_transitions",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "A write combine(merge) in write data buffer.",
-               "ConfigCode": "0x16",
-               "EventName": "write_combine",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "A Write-After-Read hazard.",
-               "ConfigCode": "0x17",
-               "EventName": "war_hazard",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "A Read-After-Write hazard.",
-               "ConfigCode": "0x18",
-               "EventName": "raw_hazard",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "A Write-After-Write hazard.",
-               "ConfigCode": "0x19",
-               "EventName": "waw_hazard",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "Rank0 enters self-refresh(SRE).",
-               "ConfigCode": "0x1A",
-               "EventName": "op_is_enter_selfref_rk0",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "Rank1 enters self-refresh(SRE).",
-               "ConfigCode": "0x1B",
-               "EventName": "op_is_enter_selfref_rk1",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "Rank2 enters self-refresh(SRE).",
-               "ConfigCode": "0x1C",
-               "EventName": "op_is_enter_selfref_rk2",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "Rank3 enters self-refresh(SRE).",
-               "ConfigCode": "0x1D",
-               "EventName": "op_is_enter_selfref_rk3",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "Rank0 enters power-down(PDE).",
-               "ConfigCode": "0x1E",
-               "EventName": "op_is_enter_powerdown_rk0",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "Rank1 enters power-down(PDE).",
-               "ConfigCode": "0x1F",
-               "EventName": "op_is_enter_powerdown_rk1",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "Rank2 enters power-down(PDE).",
-               "ConfigCode": "0x20",
-               "EventName": "op_is_enter_powerdown_rk2",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "Rank3 enters power-down(PDE).",
-               "ConfigCode": "0x21",
-               "EventName": "op_is_enter_powerdown_rk3",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "A cycle that Rank0 stays in self-refresh mode.",
-               "ConfigCode": "0x26",
-               "EventName": "selfref_mode_rk0",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "A cycle that Rank1 stays in self-refresh mode.",
-               "ConfigCode": "0x27",
-               "EventName": "selfref_mode_rk1",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "A cycle that Rank2 stays in self-refresh mode.",
-               "ConfigCode": "0x28",
-               "EventName": "selfref_mode_rk2",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "A cycle that Rank3 stays in self-refresh mode.",
-               "ConfigCode": "0x29",
-               "EventName": "selfref_mode_rk3",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "An auto-refresh(REF) command to DRAM.",
-               "ConfigCode": "0x2A",
-               "EventName": "op_is_refresh",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "A critical auto-refresh(REF) command to DRAM.",
-               "ConfigCode": "0x2B",
-               "EventName": "op_is_crit_ref",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "An MRR or MRW command to DRAM.",
-               "ConfigCode": "0x2D",
-               "EventName": "op_is_load_mode",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "A ZQCal command to DRAM.",
-               "ConfigCode": "0x2E",
-               "EventName": "op_is_zqcl",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "At least one entry in read queue reaches the visible window limit.",
-               "ConfigCode": "0x30",
-               "EventName": "visible_window_limit_reached_rd",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "At least one entry in write queue reaches the visible window limit.",
-               "ConfigCode": "0x31",
-               "EventName": "visible_window_limit_reached_wr",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "A DQS Oscillator MPC command to DRAM.",
-               "ConfigCode": "0x34",
-               "EventName": "op_is_dqsosc_mpc",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "A DQS Oscillator MRR command to DRAM.",
-               "ConfigCode": "0x35",
-               "EventName": "op_is_dqsosc_mrr",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "A Temperature Compensated Refresh(TCR) MRR command to DRAM.",
-               "ConfigCode": "0x36",
-               "EventName": "op_is_tcr_mrr",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "A ZQCal Start command to DRAM.",
-               "ConfigCode": "0x37",
-               "EventName": "op_is_zqstart",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "A ZQCal Latch command to DRAM.",
-               "ConfigCode": "0x38",
-               "EventName": "op_is_zqlatch",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "A packet at CHI TXREQ interface (request).",
-               "ConfigCode": "0x39",
-               "EventName": "chi_txreq",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "A packet at CHI TXDAT interface (read data).",
-               "ConfigCode": "0x3A",
-               "EventName": "chi_txdat",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "A packet at CHI RXDAT interface (write data).",
-               "ConfigCode": "0x3B",
-               "EventName": "chi_rxdat",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "A packet at CHI RXRSP interface.",
-               "ConfigCode": "0x3C",
-               "EventName": "chi_rxrsp",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "A violation detected in TZC.",
-               "ConfigCode": "0x3D",
-               "EventName": "tsz_vio",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "BriefDescription": "The ddr cycles.",
-               "ConfigCode": "0x80",
-               "EventName": "ddr_cycles",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       }
-]

diff --git a/tools/perf/pmu-events/arch/arm64/freescale/yitian710/sys/metrics.json b/tools/perf/pmu-events/arch/arm64/freescale/yitian710/sys/metrics.json
deleted file mode 100644 (file)
index bc865b3..0000000
--- a/tools/perf/pmu-events/arch/arm64/freescale/yitian710/sys/metrics.json
+++ /dev/null
@@ -1,20 +0,0 @@
-[
-       {
-               "MetricName": "ddr_read_bandwidth.all",
-               "BriefDescription": "The ddr read bandwidth(MB/s).",
-               "MetricGroup": "ali_drw",
-               "MetricExpr": "hif_rd * 64 / 1e6 / duration_time",
-               "ScaleUnit": "1MB/s",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       },
-       {
-               "MetricName": "ddr_write_bandwidth.all",
-               "BriefDescription": "The ddr write bandwidth(MB/s).",
-               "MetricGroup": "ali_drw",
-               "MetricExpr": "(hif_wr + hif_rmw) * 64 / 1e6 / duration_time",
-               "ScaleUnit": "1MB/s",
-               "Unit": "ali_drw",
-               "Compat": "ali_drw_pmu"
-       }
-]

diff --git a/tools/perf/pmu-events/arch/arm64/thead/yitian710/sys/ali_drw.json b/tools/perf/pmu-events/arch/arm64/thead/yitian710/sys/ali_drw.json
new file mode 100644 (file)
index 0000000..e21c469
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/thead/yitian710/sys/ali_drw.json
@@ -0,0 +1,373 @@
+[
+       {
+               "BriefDescription": "A Write or Read Op at HIF interface. The unit is 64B.",
+               "ConfigCode": "0x0",
+               "EventName": "hif_rd_or_wr",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "A Write Op at HIF interface. The unit is 64B.",
+               "ConfigCode": "0x1",
+               "EventName": "hif_wr",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "A Read Op at HIF interface. The unit is 64B.",
+               "ConfigCode": "0x2",
+               "EventName": "hif_rd",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "A Read-Modify-Write Op at HIF interface. The unit is 64B.",
+               "ConfigCode": "0x3",
+               "EventName": "hif_rmw",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "A high priority Read at HIF interface. The unit is 64B.",
+               "ConfigCode": "0x4",
+               "EventName": "hif_hi_pri_rd",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "A write data cycle at DFI interface (to DRAM).",
+               "ConfigCode": "0x7",
+               "EventName": "dfi_wr_data_cycles",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "A read data cycle at DFI interface (to DRAM).",
+               "ConfigCode": "0x8",
+               "EventName": "dfi_rd_data_cycles",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "A high priority read becomes critical.",
+               "ConfigCode": "0x9",
+               "EventName": "hpr_xact_when_critical",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "A low priority read becomes critical.",
+               "ConfigCode": "0xA",
+               "EventName": "lpr_xact_when_critical",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "A write becomes critical.",
+               "ConfigCode": "0xB",
+               "EventName": "wr_xact_when_critical",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "An Activate(ACT) command to DRAM.",
+               "ConfigCode": "0xC",
+               "EventName": "op_is_activate",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "A Read or Write CAS command to DRAM.",
+               "ConfigCode": "0xD",
+               "EventName": "op_is_rd_or_wr",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "An Activate(ACT) command for read to DRAM.",
+               "ConfigCode": "0xE",
+               "EventName": "op_is_rd_activate",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "A Read CAS command to DRAM.",
+               "ConfigCode": "0xF",
+               "EventName": "op_is_rd",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "A Write CAS command to DRAM.",
+               "ConfigCode": "0x10",
+               "EventName": "op_is_wr",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "A Masked Write command to DRAM.",
+               "ConfigCode": "0x11",
+               "EventName": "op_is_mwr",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "A Precharge(PRE) command to DRAM.",
+               "ConfigCode": "0x12",
+               "EventName": "op_is_precharge",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "A Precharge(PRE) required by read or write.",
+               "ConfigCode": "0x13",
+               "EventName": "precharge_for_rdwr",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "A Precharge(PRE) required by other conditions.",
+               "ConfigCode": "0x14",
+               "EventName": "precharge_for_other",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "A read-write turnaround.",
+               "ConfigCode": "0x15",
+               "EventName": "rdwr_transitions",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "A write combine(merge) in write data buffer.",
+               "ConfigCode": "0x16",
+               "EventName": "write_combine",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "A Write-After-Read hazard.",
+               "ConfigCode": "0x17",
+               "EventName": "war_hazard",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "A Read-After-Write hazard.",
+               "ConfigCode": "0x18",
+               "EventName": "raw_hazard",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "A Write-After-Write hazard.",
+               "ConfigCode": "0x19",
+               "EventName": "waw_hazard",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "Rank0 enters self-refresh(SRE).",
+               "ConfigCode": "0x1A",
+               "EventName": "op_is_enter_selfref_rk0",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "Rank1 enters self-refresh(SRE).",
+               "ConfigCode": "0x1B",
+               "EventName": "op_is_enter_selfref_rk1",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "Rank2 enters self-refresh(SRE).",
+               "ConfigCode": "0x1C",
+               "EventName": "op_is_enter_selfref_rk2",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "Rank3 enters self-refresh(SRE).",
+               "ConfigCode": "0x1D",
+               "EventName": "op_is_enter_selfref_rk3",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "Rank0 enters power-down(PDE).",
+               "ConfigCode": "0x1E",
+               "EventName": "op_is_enter_powerdown_rk0",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "Rank1 enters power-down(PDE).",
+               "ConfigCode": "0x1F",
+               "EventName": "op_is_enter_powerdown_rk1",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "Rank2 enters power-down(PDE).",
+               "ConfigCode": "0x20",
+               "EventName": "op_is_enter_powerdown_rk2",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "Rank3 enters power-down(PDE).",
+               "ConfigCode": "0x21",
+               "EventName": "op_is_enter_powerdown_rk3",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "A cycle that Rank0 stays in self-refresh mode.",
+               "ConfigCode": "0x26",
+               "EventName": "selfref_mode_rk0",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "A cycle that Rank1 stays in self-refresh mode.",
+               "ConfigCode": "0x27",
+               "EventName": "selfref_mode_rk1",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "A cycle that Rank2 stays in self-refresh mode.",
+               "ConfigCode": "0x28",
+               "EventName": "selfref_mode_rk2",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "A cycle that Rank3 stays in self-refresh mode.",
+               "ConfigCode": "0x29",
+               "EventName": "selfref_mode_rk3",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "An auto-refresh(REF) command to DRAM.",
+               "ConfigCode": "0x2A",
+               "EventName": "op_is_refresh",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "A critical auto-refresh(REF) command to DRAM.",
+               "ConfigCode": "0x2B",
+               "EventName": "op_is_crit_ref",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "An MRR or MRW command to DRAM.",
+               "ConfigCode": "0x2D",
+               "EventName": "op_is_load_mode",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "A ZQCal command to DRAM.",
+               "ConfigCode": "0x2E",
+               "EventName": "op_is_zqcl",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "At least one entry in read queue reaches the visible window limit.",
+               "ConfigCode": "0x30",
+               "EventName": "visible_window_limit_reached_rd",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "At least one entry in write queue reaches the visible window limit.",
+               "ConfigCode": "0x31",
+               "EventName": "visible_window_limit_reached_wr",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "A DQS Oscillator MPC command to DRAM.",
+               "ConfigCode": "0x34",
+               "EventName": "op_is_dqsosc_mpc",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "A DQS Oscillator MRR command to DRAM.",
+               "ConfigCode": "0x35",
+               "EventName": "op_is_dqsosc_mrr",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "A Temperature Compensated Refresh(TCR) MRR command to DRAM.",
+               "ConfigCode": "0x36",
+               "EventName": "op_is_tcr_mrr",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "A ZQCal Start command to DRAM.",
+               "ConfigCode": "0x37",
+               "EventName": "op_is_zqstart",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "A ZQCal Latch command to DRAM.",
+               "ConfigCode": "0x38",
+               "EventName": "op_is_zqlatch",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "A packet at CHI TXREQ interface (request).",
+               "ConfigCode": "0x39",
+               "EventName": "chi_txreq",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "A packet at CHI TXDAT interface (read data).",
+               "ConfigCode": "0x3A",
+               "EventName": "chi_txdat",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "A packet at CHI RXDAT interface (write data).",
+               "ConfigCode": "0x3B",
+               "EventName": "chi_rxdat",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "A packet at CHI RXRSP interface.",
+               "ConfigCode": "0x3C",
+               "EventName": "chi_rxrsp",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "A violation detected in TZC.",
+               "ConfigCode": "0x3D",
+               "EventName": "tsz_vio",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "BriefDescription": "The ddr cycles.",
+               "ConfigCode": "0x80",
+               "EventName": "ddr_cycles",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       }
+]

diff --git a/tools/perf/pmu-events/arch/arm64/thead/yitian710/sys/metrics.json b/tools/perf/pmu-events/arch/arm64/thead/yitian710/sys/metrics.json
new file mode 100644 (file)
index 0000000..bc865b3
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/thead/yitian710/sys/metrics.json
@@ -0,0 +1,20 @@
+[
+       {
+               "MetricName": "ddr_read_bandwidth.all",
+               "BriefDescription": "The ddr read bandwidth(MB/s).",
+               "MetricGroup": "ali_drw",
+               "MetricExpr": "hif_rd * 64 / 1e6 / duration_time",
+               "ScaleUnit": "1MB/s",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       },
+       {
+               "MetricName": "ddr_write_bandwidth.all",
+               "BriefDescription": "The ddr write bandwidth(MB/s).",
+               "MetricGroup": "ali_drw",
+               "MetricExpr": "(hif_wr + hif_rmw) * 64 / 1e6 / duration_time",
+               "ScaleUnit": "1MB/s",
+               "Unit": "ali_drw",
+               "Compat": "ali_drw_pmu"
+       }
+]