drm/vc4: hdmi: Enforce the minimum rate at runtime_resume
authorMaxime Ripard <maxime@cerno.tech>
Thu, 29 Sep 2022 09:21:17 +0000 (11:21 +0200)
committerMaxime Ripard <maxime@cerno.tech>
Thu, 13 Oct 2022 11:56:52 +0000 (13:56 +0200)
This is a revert of commit fd5894fa2413 ("drm/vc4: hdmi: Remove clock
rate initialization"), with the code slightly moved around.

It turns out that we can't downright remove that code from the driver,
since the Pi0-3 and Pi4 are in different cases, and it only works for
the Pi4.

Indeed, the commit mentioned above was relying on the RaspberryPi
firmware clocks driver to initialize the rate if it wasn't done by the
firmware. However, the Pi0-3 are using the clk-bcm2835 clock driver that
wasn't doing this initialization. We therefore end up with the clock not
being assigned a rate, and the CPU stalling when trying to access a
register.

We can't move that initialization in the clk-bcm2835 driver, since the
HSM clock we depend on is actually part of the HDMI power domain, so any
rate setup is only valid when the power domain is enabled. Thus, we
reinstated the minimum rate setup at runtime_suspend, which should
address both issues.

Link: https://lore.kernel.org/dri-devel/20220922145448.w3xfywkn5ecak2et@pengutronix.de/
Fixes: fd5894fa2413 ("drm/vc4: hdmi: Remove clock rate initialization")
Reported-by: Marc Kleine-Budde <mkl@pengutronix.de>
Reviewed-by: Javier Martinez Canillas <javierm@redhat.com>
Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://patchwork.freedesktop.org/patch/msgid/20220929-rpi-pi3-unplugged-fixes-v1-1-cd22e962296c@cerno.tech
drivers/gpu/drm/vc4/vc4_hdmi.c

index 1e5f68704d7d8b73a3d16f70d0bfe300243b26ac..780a19a75c3f52f8b7037942f8ff9369fcc52448 100644 (file)
@@ -2871,6 +2871,15 @@ static int vc4_hdmi_runtime_resume(struct device *dev)
        u32 __maybe_unused value;
        int ret;
 
+       /*
+        * The HSM clock is in the HDMI power domain, so we need to set
+        * its frequency while the power domain is active so that it
+        * keeps its rate.
+        */
+       ret = clk_set_min_rate(vc4_hdmi->hsm_clock, HSM_MIN_CLOCK_FREQ);
+       if (ret)
+               return ret;
+
        ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
        if (ret)
                return ret;