octeontx2-af: cn10k: Set cache lines for NPA batch alloc

Set NPA batch allocation engine to process 35 cache lines
per turn on CN10k platform.

Signed-off-by: Geetha sowjanya <gakula@marvell.com>
Signed-off-by: Sunil Goutham <sgoutham@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
index add4a39edced5d803b4b9762861959f7fb9541e5..d8f5e61f0304f0507d5a2d9a50f3b05bd9852c0f 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
@@ -594,6 +594,7 @@ struct npa_lf_alloc_rsp {
        u32 stack_pg_ptrs;  /* No of ptrs per stack page */
        u32 stack_pg_bytes; /* Size of stack page */
        u16 qints; /* NPA_AF_CONST::QINTS */
+       u8 cache_lines; /*BATCH ALLOC DMA */
 };
 
 /* NPA AQ enqueue msg */

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c
index 24c2bfdfec4e55d367496f1870a070a8a02061ae..f046f2e4256a5ef1b8ed944c92c4b90b6a3ba26d 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c
@@ -419,6 +419,10 @@ exit:
        rsp->stack_pg_ptrs = (cfg >> 8) & 0xFF;
        rsp->stack_pg_bytes = cfg & 0xFF;
        rsp->qints = (cfg >> 28) & 0xFFF;
+       if (!is_rvu_otx2(rvu)) {
+               cfg = rvu_read64(rvu, block->addr, NPA_AF_BATCH_CTL);
+               rsp->cache_lines = (cfg >> 1) & 0x3F;
+       }
        return rc;
 }
 
@@ -478,6 +482,13 @@ static int npa_aq_init(struct rvu *rvu, struct rvu_block *block)
 #endif
        rvu_write64(rvu, block->addr, NPA_AF_NDC_CFG, cfg);
 
+       /* For CN10K NPA BATCH DMA set 35 cache lines */
+       if (!is_rvu_otx2(rvu)) {
+               cfg = rvu_read64(rvu, block->addr, NPA_AF_BATCH_CTL);
+               cfg &= ~0x7EULL;
+               cfg |= BIT_ULL(6) | BIT_ULL(2) | BIT_ULL(1);
+               rvu_write64(rvu, block->addr, NPA_AF_BATCH_CTL, cfg);
+       }
        /* Result structure can be followed by Aura/Pool context at
         * RES + 128bytes and a write mask at RES + 256 bytes, depending on
         * operation type. Alloc sufficient result memory for all operations.

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h
index 960ee1c2e178be94a431c81a11aa8508a58cf36d..4600c31b336bdfcbcdcd52a1f4156803f8fce9cd 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h
@@ -156,6 +156,7 @@
 #define NPA_AF_AQ_DONE_INT_W1S          (0x0688)
 #define NPA_AF_AQ_DONE_ENA_W1S          (0x0690)
 #define NPA_AF_AQ_DONE_ENA_W1C          (0x0698)
+#define NPA_AF_BATCH_CTL               (0x06a0)
 #define NPA_AF_LFX_AURAS_CFG(a)         (0x4000 | (a) << 18)
 #define NPA_AF_LFX_LOC_AURAS_BASE(a)    (0x4010 | (a) << 18)
 #define NPA_AF_LFX_QINTS_CFG(a)         (0x4100 | (a) << 18)