platform/x86: mlx-platform: Add more definitions for system attributes

Add new attributes for the all type systems specifying for each
equipped CPLD device, the CPLD part number and the CPLD minor version
of the device: 'cpld{n}_pn' and 'cpld{n}_version_min'.
This information is to be used for mathcing the current CPLD image and
for making decision if image upgrade is required for CPLD device.

Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c
index c27548fd386acf5b0486975584a26194e0134909..034736cec9a6ff43eef191dc3d4a854586953fcf 100644 (file)
--- a/drivers/platform/x86/mlx-platform.c
+++ b/drivers/platform/x86/mlx-platform.c
@@ -26,6 +26,10 @@
 #define MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET  0x01
 #define MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET  0x02
 #define MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET  0x03
+#define MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET   0x04
+#define MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET   0x06
+#define MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET   0x08
+#define MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET   0x0a
 #define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET        0x1d
 #define MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET 0x1e
 #define MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET 0x1f
@@ -72,6 +76,10 @@
 #define MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET    0xd1
 #define MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET  0xd2
 #define MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET    0xd3
+#define MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET 0xde
+#define MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET 0xdf
+#define MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET 0xe0
+#define MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET 0xe1
 #define MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET        0xe2
 #define MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET       0xe3
 #define MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET     0xe4
@@ -1303,6 +1311,32 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_regs_io_data[] = {
                .bit = GENMASK(7, 0),
                .mode = 0444,
        },
+       {
+               .label = "cpld1_pn",
+               .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET,
+               .bit = GENMASK(15, 0),
+               .mode = 0444,
+               .regnum = 2,
+       },
+       {
+               .label = "cpld2_pn",
+               .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET,
+               .bit = GENMASK(15, 0),
+               .mode = 0444,
+               .regnum = 2,
+       },
+       {
+               .label = "cpld1_version_min",
+               .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET,
+               .bit = GENMASK(7, 0),
+               .mode = 0444,
+       },
+       {
+               .label = "cpld2_version_min",
+               .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET,
+               .bit = GENMASK(7, 0),
+               .mode = 0444,
+       },
        {
                .label = "reset_long_pb",
                .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
@@ -1409,6 +1443,32 @@ static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_regs_io_data[] = {
                .bit = GENMASK(7, 0),
                .mode = 0444,
        },
+       {
+               .label = "cpld1_pn",
+               .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET,
+               .bit = GENMASK(15, 0),
+               .mode = 0444,
+               .regnum = 2,
+       },
+       {
+               .label = "cpld2_pn",
+               .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET,
+               .bit = GENMASK(15, 0),
+               .mode = 0444,
+               .regnum = 2,
+       },
+       {
+               .label = "cpld1_version_min",
+               .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET,
+               .bit = GENMASK(7, 0),
+               .mode = 0444,
+       },
+       {
+               .label = "cpld2_version_min",
+               .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET,
+               .bit = GENMASK(7, 0),
+               .mode = 0444,
+       },
        {
                .label = "reset_long_pb",
                .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
@@ -1527,6 +1587,58 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
                .bit = GENMASK(7, 0),
                .mode = 0444,
        },
+       {
+               .label = "cpld1_pn",
+               .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET,
+               .bit = GENMASK(15, 0),
+               .mode = 0444,
+               .regnum = 2,
+       },
+       {
+               .label = "cpld2_pn",
+               .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET,
+               .bit = GENMASK(15, 0),
+               .mode = 0444,
+               .regnum = 2,
+       },
+       {
+               .label = "cpld3_pn",
+               .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET,
+               .bit = GENMASK(15, 0),
+               .mode = 0444,
+               .regnum = 2,
+       },
+       {
+               .label = "cpld4_pn",
+               .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET,
+               .bit = GENMASK(15, 0),
+               .mode = 0444,
+               .regnum = 2,
+       },
+       {
+               .label = "cpld1_version_min",
+               .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET,
+               .bit = GENMASK(7, 0),
+               .mode = 0444,
+       },
+       {
+               .label = "cpld2_version_min",
+               .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET,
+               .bit = GENMASK(7, 0),
+               .mode = 0444,
+       },
+       {
+               .label = "cpld3_version_min",
+               .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET,
+               .bit = GENMASK(7, 0),
+               .mode = 0444,
+       },
+       {
+               .label = "cpld4_version_min",
+               .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET,
+               .bit = GENMASK(7, 0),
+               .mode = 0444,
+       },
        {
                .label = "reset_long_pb",
                .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
@@ -2006,6 +2118,10 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
        case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET:
        case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET:
        case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET:
+       case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET:
+       case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET:
+       case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET:
+       case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET:
        case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
        case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:
        case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET:
@@ -2051,6 +2167,10 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
        case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET:
        case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET:
        case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET:
+       case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET:
+       case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET:
+       case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET:
+       case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET:
        case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:
        case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET:
        case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET:
@@ -2085,6 +2205,10 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
        case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET:
        case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET:
        case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET:
+       case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET:
+       case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET:
+       case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET:
+       case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET:
        case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
        case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:
        case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET:
@@ -2122,6 +2246,10 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
        case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET:
        case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET:
        case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET:
+       case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET:
+       case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET:
+       case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET:
+       case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET:
        case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:
        case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET:
        case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET: