rtw88: coex: 8821c: correct antenna switch function
authorGuo-Feng Fan <vincent_fann@realtek.com>
Tue, 2 Feb 2021 05:50:10 +0000 (13:50 +0800)
committerKalle Valo <kvalo@codeaurora.org>
Mon, 8 Feb 2021 10:51:31 +0000 (12:51 +0200)
This patch fixes a defect that uses incorrect function to access
registers. Use 8 and 32 bit access function to access 8 and 32 bit long
data respectively.

Signed-off-by: Guo-Feng Fan <vincent_fann@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/20210202055012.8296-2-pkshih@realtek.com
drivers/net/wireless/realtek/rtw88/rtw8821c.c

index 74155c999ebb42b298a2b7abf16f90d7523e110e..8f53afb678704b20fe286bc4500a17614cd71788 100644 (file)
@@ -719,8 +719,8 @@ static void rtw8821c_coex_cfg_ant_switch(struct rtw_dev *rtwdev, u8 ctrl_type,
                        regval = (!polarity_inverse ? 0x1 : 0x2);
                }
 
-               rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_R_RFE_SEL_15,
-                               regval);
+               rtw_write32_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_R_RFE_SEL_15,
+                                regval);
                break;
        case COEX_SWITCH_CTRL_BY_PTA:
                rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
@@ -730,8 +730,8 @@ static void rtw8821c_coex_cfg_ant_switch(struct rtw_dev *rtwdev, u8 ctrl_type,
                                PTA_CTRL_PIN);
 
                regval = (!polarity_inverse ? 0x2 : 0x1);
-               rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_R_RFE_SEL_15,
-                               regval);
+               rtw_write32_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_R_RFE_SEL_15,
+                                regval);
                break;
        case COEX_SWITCH_CTRL_BY_ANTDIV:
                rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
@@ -757,11 +757,11 @@ static void rtw8821c_coex_cfg_ant_switch(struct rtw_dev *rtwdev, u8 ctrl_type,
        }
 
        if (ctrl_type == COEX_SWITCH_CTRL_BY_BT) {
-               rtw_write32_clr(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE1);
-               rtw_write32_clr(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE2);
+               rtw_write8_clr(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE1);
+               rtw_write8_clr(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE2);
        } else {
-               rtw_write32_set(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE1);
-               rtw_write32_set(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE2);
+               rtw_write8_set(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE1);
+               rtw_write8_set(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE2);
        }
 }