dt-bindings: clock: renesas,r9a09g057-cpg: Add USB2 PHY and GBETH PTP core clocks

Add definitions for USB2 PHY core clocks and Gigabit Ethernet PTP
reference core clocks in the R9A09G057 CPG DT bindings header file.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407165202.197570-8-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/include/dt-bindings/clock/renesas,r9a09g057-cpg.h b/include/dt-bindings/clock/renesas,r9a09g057-cpg.h
index 541e6d719bd63c0764df26d760c2c7d1cb4c3dd6..884dbeb1e139ff2f6ab0fb5a03fde12f7d1ac514 100644 (file)
--- a/include/dt-bindings/clock/renesas,r9a09g057-cpg.h
+++ b/include/dt-bindings/clock/renesas,r9a09g057-cpg.h
@@ -17,5 +17,9 @@
 #define R9A09G057_CM33_CLK0                    6
 #define R9A09G057_CST_0_SWCLKTCK               7
 #define R9A09G057_IOTOP_0_SHCLK                        8
+#define R9A09G057_USB2_0_CLK_CORE0             9
+#define R9A09G057_USB2_0_CLK_CORE1             10
+#define R9A09G057_GBETH_0_CLK_PTP_REF_I                11
+#define R9A09G057_GBETH_1_CLK_PTP_REF_I                12
 
 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ */