drm/amdgpu/mes: update hqd masks when disable_kq is set

Make all resources available to user queues.

Reviewed-by: Prike Liang <Prike.Liang@amd.com>
Suggested-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Sunil Khatri <sunil.khatri@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index c52071841226febe47b21dfb2b031ccc18c8dc07..4127e11924d8d42ce675d38721d21a6d09e4acfa 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -124,14 +124,14 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
                         * Set GFX pipe 0 queue 1-7 for MES scheduling
                         * mask = 1111 1110b
                         */
-                       adev->mes.gfx_hqd_mask[i] = 0xFE;
+                       adev->mes.gfx_hqd_mask[i] = adev->gfx.disable_kq ? 0xFF : 0xFE;
                else
                        /*
                         * GFX pipe 0 queue 0 is being used by Kernel queue.
                         * Set GFX pipe 0 queue 1 for MES scheduling
                         * mask = 10b
                         */
-                       adev->mes.gfx_hqd_mask[i] = 0x2;
+                       adev->mes.gfx_hqd_mask[i] = adev->gfx.disable_kq ? 0x3 : 0x2;
        }
 
        num_pipes = adev->gfx.mec.num_pipe_per_mec * adev->gfx.mec.num_mec;
@@ -142,7 +142,7 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
        for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) {
                if (i >= num_pipes)
                        break;
-               adev->mes.compute_hqd_mask[i] = 0xc;
+               adev->mes.compute_hqd_mask[i] = adev->gfx.disable_kq ? 0xF : 0xC;
        }
 
        num_pipes = adev->sdma.num_instances;