On Radxa A5E board, the EMAC0 connect to external Maxio MAE0621A PHY,
which features a 25MHz crystal, and using PH8 pin as PHY reset.
Tested on A5E board with schematic V1.20.
Tested-by: Corentin LABBE <clabbe.montjoie@gmail.com>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
Link: https://patch.msgid.link/20250430-01-sun55i-emac0-v3-4-6fc000bbccbd@gentoo.org
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
compatible = "radxa,cubie-a5e", "allwinner,sun55i-a527";
aliases {
+ ethernet0 = &emac0;
serial0 = &uart0;
};
status = "okay";
};
+&emac0 {
+ phy-mode = "rgmii-id";
+ phy-handle = <&ext_rgmii_phy>;
+ phy-supply = <®_cldo3>;
+
+ allwinner,tx-delay-ps = <300>;
+ allwinner,rx-delay-ps = <400>;
+
+ status = "okay";
+};
+
+&mdio0 {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
&mmc0 {
vmmc-supply = <®_cldo3>;
cd-gpios = <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */