arm64: dts: allwinner: a527: add EMAC0 to Radxa A5E board
authorYixun Lan <dlan@gentoo.org>
Wed, 30 Apr 2025 05:32:06 +0000 (13:32 +0800)
committerChen-Yu Tsai <wens@csie.org>
Fri, 2 May 2025 17:29:06 +0000 (01:29 +0800)
On Radxa A5E board, the EMAC0 connect to external Maxio MAE0621A PHY,
which features a 25MHz crystal, and using PH8 pin as PHY reset.

Tested on A5E board with schematic V1.20.

Tested-by: Corentin LABBE <clabbe.montjoie@gmail.com>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
Link: https://patch.msgid.link/20250430-01-sun55i-emac0-v3-4-6fc000bbccbd@gentoo.org
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts

index 2d2f3af91d05e78c010b5c412b91105b1cbd6f63..0f58d92a6adcd6902d28cdfdabbec86c14eceb77 100644 (file)
@@ -12,6 +12,7 @@
        compatible = "radxa,cubie-a5e", "allwinner,sun55i-a527";
 
        aliases {
+               ethernet0 = &emac0;
                serial0 = &uart0;
        };
 
        status = "okay";
 };
 
+&emac0 {
+       phy-mode = "rgmii-id";
+       phy-handle = <&ext_rgmii_phy>;
+       phy-supply = <&reg_cldo3>;
+
+       allwinner,tx-delay-ps = <300>;
+       allwinner,rx-delay-ps = <400>;
+
+       status = "okay";
+};
+
+&mdio0 {
+       ext_rgmii_phy: ethernet-phy@1 {
+               compatible = "ethernet-phy-ieee802.3-c22";
+               reg = <1>;
+       };
+};
+
 &mmc0 {
        vmmc-supply = <&reg_cldo3>;
        cd-gpios = <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */