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RISC-V: Fix counter restart during overflow for RV32
author
Atish Patra
<atishp@rivosinc.com>
Mon, 11 Jul 2022 17:46:28 +0000
(10:46 -0700)
committer
Palmer Dabbelt
<palmer@rivosinc.com>
Thu, 11 Aug 2022 21:58:07 +0000
(14:58 -0700)
Pass the upper half of the initial value of the counter correctly
for RV32.
Fixes:
4905ec2fb7e6
("RISC-V: Add sscofpmf extension support")
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Cc: stable@vger.kernel.org
Link:
https://lore.kernel.org/r/20220711174632.4186047-2-atishp@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
drivers/perf/riscv_pmu_sbi.c
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diff --git
a/drivers/perf/riscv_pmu_sbi.c
b/drivers/perf/riscv_pmu_sbi.c
index dca3537a8dccea33ed61e070138e31a8588b9adc..0cb694b794ae8b3309503a44b5ca0c6be8abfc5f 100644
(file)
--- a/
drivers/perf/riscv_pmu_sbi.c
+++ b/
drivers/perf/riscv_pmu_sbi.c
@@
-525,8
+525,13
@@
static inline void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu,
hwc = &event->hw;
max_period = riscv_pmu_ctr_get_width_mask(event);
init_val = local64_read(&hwc->prev_count) & max_period;
+#if defined(CONFIG_32BIT)
+ sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1,
+ flag, init_val, init_val >> 32, 0);
+#else
sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1,
flag, init_val, 0, 0);
+#endif
}
ctr_ovf_mask = ctr_ovf_mask >> 1;
idx++;