s390/disassembler: Add instructions

Add more instructions to the kernel disassembler.

Reviewed-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Heiko Carstens <hca@linux.ibm.com>
Signed-off-by: Vasily Gorbik <gor@linux.ibm.com>

diff --git a/arch/s390/kernel/dis.c b/arch/s390/kernel/dis.c
index 117fb75913d7b16175952172e8bbb3223b395116..cc7e905d0ff4a717baf9a8aca97071d73557aa87 100644 (file)
--- a/arch/s390/kernel/dis.c
+++ b/arch/s390/kernel/dis.c
@@ -122,6 +122,7 @@ enum {
        U8_32,  /* 8 bit unsigned value starting at 32 */
        U12_16, /* 12 bit unsigned value starting at 16 */
        U16_16, /* 16 bit unsigned value starting at 16 */
+       U16_20, /* 16 bit unsigned value starting at 20 */
        U16_32, /* 16 bit unsigned value starting at 32 */
        U32_16, /* 32 bit unsigned value starting at 16 */
        VX_12,  /* Vector index register starting at position 12 */
@@ -184,6 +185,7 @@ static const struct s390_operand operands[] = {
        [U8_32]  = {  8, 32, 0 },
        [U12_16] = { 12, 16, 0 },
        [U16_16] = { 16, 16, 0 },
+       [U16_20] = { 16, 20, 0 },
        [U16_32] = { 16, 32, 0 },
        [U32_16] = { 32, 16, 0 },
        [VX_12]  = {  4, 12, OPERAND_INDEX | OPERAND_VR },
@@ -300,14 +302,17 @@ static const unsigned char formats[][6] = {
        [INSTR_VRI_V0UU2]    = { V_8, U16_16, U4_32, 0, 0, 0 },
        [INSTR_VRI_V0UUU]    = { V_8, U8_16, U8_24, U4_32, 0, 0 },
        [INSTR_VRI_VR0UU]    = { V_8, R_12, U8_28, U4_24, 0, 0 },
+       [INSTR_VRI_VV0UU]    = { V_8, V_12, U8_28, U4_24, 0, 0 },
        [INSTR_VRI_VVUU]     = { V_8, V_12, U16_16, U4_32, 0, 0 },
        [INSTR_VRI_VVUUU]    = { V_8, V_12, U12_16, U4_32, U4_28, 0 },
        [INSTR_VRI_VVUUU2]   = { V_8, V_12, U8_28, U8_16, U4_24, 0 },
        [INSTR_VRI_VVV0U]    = { V_8, V_12, V_16, U8_24, 0, 0 },
        [INSTR_VRI_VVV0UU]   = { V_8, V_12, V_16, U8_24, U4_32, 0 },
        [INSTR_VRI_VVV0UU2]  = { V_8, V_12, V_16, U8_28, U4_24, 0 },
-       [INSTR_VRR_0V]       = { V_12, 0, 0, 0, 0, 0 },
+       [INSTR_VRI_VVV0UV]   = { V_8, V_12, V_16, V_32, U8_24, 0 },
+       [INSTR_VRR_0V0U]     = { V_12, U16_20, 0, 0, 0, 0 },
        [INSTR_VRR_0VV0U]    = { V_12, V_16, U4_24, 0, 0, 0 },
+       [INSTR_VRR_0VVU]     = { V_12, V_16, U16_20, 0, 0, 0 },
        [INSTR_VRR_RV0UU]    = { R_8, V_12, U4_24, U4_28, 0, 0 },
        [INSTR_VRR_VRR]      = { V_8, R_12, R_16, 0, 0, 0 },
        [INSTR_VRR_VV]       = { V_8, V_12, 0, 0, 0, 0 },

diff --git a/arch/s390/tools/opcodes.txt b/arch/s390/tools/opcodes.txt
index aada7aa9ada2a2a9f0fc6e04df30984d3bdbc2fe..b781e1f05c9af3f42c39d3406741923ae4d2d6aa 100644 (file)
--- a/arch/s390/tools/opcodes.txt
+++ b/arch/s390/tools/opcodes.txt
@@ -528,8 +528,8 @@ b939        dfltcc  RRF_R0RR2
 b93a   kdsa    RRE_RR
 b93b   nnpa    RRE_00
 b93c   prno    RRE_RR
-b93e   kimd    RRE_RR
-b93f   klmd    RRE_RR
+b93e   kimd    RRF_U0RR
+b93f   klmd    RRF_U0RR
 b941   cfdtr   RRF_UURF
 b942   clgdtr  RRF_UURF
 b943   clfdtr  RRF_UURF
@@ -549,6 +549,10 @@ b964       nngrk   RRF_R0RR2
 b965   ocgrk   RRF_R0RR2
 b966   nogrk   RRF_R0RR2
 b967   nxgrk   RRF_R0RR2
+b968   clzg    RRE_RR
+b969   ctzg    RRE_RR
+b96c   bextg   RRF_R0RR2
+b96d   bdepg   RRF_R0RR2
 b972   crt     RRF_U0RR
 b973   clrt    RRF_U0RR
 b974   nnrk    RRF_R0RR2
@@ -796,6 +800,16 @@ e35b       sy      RXY_RRRD
 e35c   mfy     RXY_RRRD
 e35e   aly     RXY_RRRD
 e35f   sly     RXY_RRRD
+e360   lxab    RXY_RRRD
+e361   llxab   RXY_RRRD
+e362   lxah    RXY_RRRD
+e363   llxah   RXY_RRRD
+e364   lxaf    RXY_RRRD
+e365   llxaf   RXY_RRRD
+e366   lxag    RXY_RRRD
+e367   llxag   RXY_RRRD
+e368   lxaq    RXY_RRRD
+e369   llxaq   RXY_RRRD
 e370   sthy    RXY_RRRD
 e371   lay     RXY_RRRD
 e372   stcy    RXY_RRRD
@@ -880,6 +894,8 @@ e63c        vupkz   VSI_URDV
 e63d   vstrl   VSI_URDV
 e63f   vstrlr  VRS_RRDV
 e649   vlip    VRI_V0UU2
+e64a   vcvdq   VRI_VV0UU
+e64e   vcvbq   VRR_VV0U2
 e650   vcvb    VRR_RV0UU
 e651   vclzdp  VRR_VV0U2
 e652   vcvbg   VRR_RV0UU
@@ -893,7 +909,7 @@ e65b        vpsop   VRI_VVUUU2
 e65c   vupkzl  VRR_VV0U2
 e65d   vcfn    VRR_VV0UU2
 e65e   vclfnl  VRR_VV0UU2
-e65f   vtp     VRR_0V
+e65f   vtp     VRR_0V0U
 e670   vpkzr   VRI_VVV0UU2
 e671   vap     VRI_VVV0UU2
 e672   vsrpr   VRI_VVV0UU2
@@ -908,6 +924,7 @@ e67b        vrp     VRI_VVV0UU2
 e67c   vscshp  VRR_VVV
 e67d   vcsph   VRR_VVV0U0
 e67e   vsdp    VRI_VVV0UU2
+e67f   vtz     VRR_0VVU
 e700   vleb    VRX_VRRDU
 e701   vleh    VRX_VRRDU
 e702   vleg    VRX_VRRDU
@@ -948,6 +965,7 @@ e74d        vrep    VRI_VVUU
 e750   vpopct  VRR_VV0U
 e752   vctz    VRR_VV0U
 e753   vclz    VRR_VV0U
+e754   vgem    VRR_VV0U
 e756   vlr     VRX_VV
 e75c   vistr   VRR_VV0U0U
 e75f   vseg    VRR_VV0U
@@ -985,6 +1003,8 @@ e784       vpdi    VRR_VVV0U
 e785   vbperm  VRR_VVV
 e786   vsld    VRI_VVV0U
 e787   vsrd    VRI_VVV0U
+e788   veval   VRI_VVV0UV
+e789   vblend  VRR_VVVU0V
 e78a   vstrc   VRR_VVVUU0V
 e78b   vstrs   VRR_VVVUU0V
 e78c   vperm   VRR_VVV0V
@@ -1010,6 +1030,10 @@ e7ac     vmale   VRR_VVVU0V
 e7ad   vmalo   VRR_VVVU0V
 e7ae   vmae    VRR_VVVU0V
 e7af   vmao    VRR_VVVU0V
+e7b0   vdl     VRR_VVV0UU
+e7b1   vrl     VRR_VVV0UU
+e7b2   vd      VRR_VVV0UU
+e7b3   vr      VRR_VVV0UU
 e7b4   vgfm    VRR_VVV0U
 e7b8   vmsl    VRR_VVVUU0V
 e7b9   vaccc   VRR_VVVU0V