drm/amdgpu/gfx11: properly reference EOP interrupts for userqs

Regardless of whether we disable kernel queues, we need
to take an extra reference to the pipe interrupts for
user queues to make sure they stay enabled in case we
disable them for kernel queues.

Reviewed-by: Sunil Khatri <sunil.khatri@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index ac90f823e596c9568175a2fb10045d056f9d1b2b..a528afe38e0b6bbdd1b9e064f5c89c6b783c5fba 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -4832,10 +4832,10 @@ static int gfx_v11_0_hw_init(struct amdgpu_ip_block *ip_block)
 static int gfx_v11_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
                                              bool enable)
 {
-       if (adev->gfx.disable_kq) {
-               unsigned int irq_type;
-               int m, p, r;
+       unsigned int irq_type;
+       int m, p, r;
 
+       if (adev->userq_funcs[AMDGPU_HW_IP_GFX]) {
                for (m = 0; m < adev->gfx.me.num_me; m++) {
                        for (p = 0; p < adev->gfx.me.num_pipe_per_me; p++) {
                                irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p;
@@ -4849,7 +4849,9 @@ static int gfx_v11_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
                                        return r;
                        }
                }
+       }
 
+       if (adev->userq_funcs[AMDGPU_HW_IP_COMPUTE]) {
                for (m = 0; m < adev->gfx.mec.num_mec; ++m) {
                        for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) {
                                irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
@@ -4866,6 +4868,7 @@ static int gfx_v11_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
                        }
                }
        }
+
        return 0;
 }