x86/PCI: Switch to new Intel CPU model defines

New CPU #defines encode vendor and family as well as model.

Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Link: https://lore.kernel.org/all/20240520224620.9480-30-tony.luck%40intel.com

diff --git a/arch/x86/pci/intel_mid_pci.c b/arch/x86/pci/intel_mid_pci.c
index 8edd6220660446842d28d9eb9ab0a495a89ccc66..933ff795e53ea282cb8bca20c48d51dcc1fcca4a 100644 (file)
--- a/arch/x86/pci/intel_mid_pci.c
+++ b/arch/x86/pci/intel_mid_pci.c
@@ -216,7 +216,7 @@ static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
 }
 
 static const struct x86_cpu_id intel_mid_cpu_ids[] = {
-       X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_MID, NULL),
+       X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID, NULL),
        {}
 };
 
@@ -243,7 +243,7 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev)
                model = id->model;
 
        switch (model) {
-       case INTEL_FAM6_ATOM_SILVERMONT_MID:
+       case VFM_MODEL(INTEL_ATOM_SILVERMONT_MID):
                polarity_low = false;
 
                /* Special treatment for IRQ0 */