PCI: Move pci_clear_and_set_dword() helper to PCI header

The clear and set pattern is commonly used for accessing PCI config,
move the helper pci_clear_and_set_dword() from aspm.c into PCI header.
In addition, rename to pci_clear_and_set_config_dword() to retain the
"config" information and match the other accessors.

No functional change intended.

Signed-off-by: Shuai Xue <xueshuai@linux.alibaba.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Tested-by: Ilkka Koskinen <ilkka@os.amperecomputing.com>
Link: https://lore.kernel.org/r/20231208025652.87192-4-xueshuai@linux.alibaba.com
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/drivers/pci/access.c b/drivers/pci/access.c
index 6554a2e89d3612dcb8e232802269a34c42d28e83..6449056b57dd3032b0a1fbd991f4248be0801d84 100644 (file)
--- a/drivers/pci/access.c
+++ b/drivers/pci/access.c
@@ -598,3 +598,15 @@ int pci_write_config_dword(const struct pci_dev *dev, int where,
        return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
 }
 EXPORT_SYMBOL(pci_write_config_dword);
+
+void pci_clear_and_set_config_dword(const struct pci_dev *dev, int pos,
+                                   u32 clear, u32 set)
+{
+       u32 val;
+
+       pci_read_config_dword(dev, pos, &val);
+       val &= ~clear;
+       val |= set;
+       pci_write_config_dword(dev, pos, val);
+}
+EXPORT_SYMBOL(pci_clear_and_set_config_dword);

diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index 50b04ae5c394e3691d3b100eeed3918cd7be9f4c..a720a8e3ced2005ce80eacc9e4bd71bc56ed3c2e 100644 (file)
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -426,17 +426,6 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint)
        }
 }
 
-static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos,
-                                   u32 clear, u32 set)
-{
-       u32 val;
-
-       pci_read_config_dword(pdev, pos, &val);
-       val &= ~clear;
-       val |= set;
-       pci_write_config_dword(pdev, pos, val);
-}
-
 /* Calculate L1.2 PM substate timing parameters */
 static void aspm_calc_l12_info(struct pcie_link_state *link,
                                u32 parent_l1ss_cap, u32 child_l1ss_cap)
@@ -501,10 +490,12 @@ static void aspm_calc_l12_info(struct pcie_link_state *link,
        cl1_2_enables = cctl1 & PCI_L1SS_CTL1_L1_2_MASK;
 
        if (pl1_2_enables || cl1_2_enables) {
-               pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
-                                       PCI_L1SS_CTL1_L1_2_MASK, 0);
-               pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
-                                       PCI_L1SS_CTL1_L1_2_MASK, 0);
+               pci_clear_and_set_config_dword(child,
+                                              child->l1ss + PCI_L1SS_CTL1,
+                                              PCI_L1SS_CTL1_L1_2_MASK, 0);
+               pci_clear_and_set_config_dword(parent,
+                                              parent->l1ss + PCI_L1SS_CTL1,
+                                              PCI_L1SS_CTL1_L1_2_MASK, 0);
        }
 
        /* Program T_POWER_ON times in both ports */
@@ -512,22 +503,26 @@ static void aspm_calc_l12_info(struct pcie_link_state *link,
        pci_write_config_dword(child, child->l1ss + PCI_L1SS_CTL2, ctl2);
 
        /* Program Common_Mode_Restore_Time in upstream device */
-       pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
-                               PCI_L1SS_CTL1_CM_RESTORE_TIME, ctl1);
+       pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
+                                      PCI_L1SS_CTL1_CM_RESTORE_TIME, ctl1);
 
        /* Program LTR_L1.2_THRESHOLD time in both ports */
-       pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
-                               PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
-                               PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1);
-       pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
-                               PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
-                               PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1);
+       pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
+                                      PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
+                                      PCI_L1SS_CTL1_LTR_L12_TH_SCALE,
+                                      ctl1);
+       pci_clear_and_set_config_dword(child, child->l1ss + PCI_L1SS_CTL1,
+                                      PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
+                                      PCI_L1SS_CTL1_LTR_L12_TH_SCALE,
+                                      ctl1);
 
        if (pl1_2_enables || cl1_2_enables) {
-               pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1, 0,
-                                       pl1_2_enables);
-               pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1, 0,
-                                       cl1_2_enables);
+               pci_clear_and_set_config_dword(parent,
+                                              parent->l1ss + PCI_L1SS_CTL1, 0,
+                                              pl1_2_enables);
+               pci_clear_and_set_config_dword(child,
+                                              child->l1ss + PCI_L1SS_CTL1, 0,
+                                              cl1_2_enables);
        }
 }
 
@@ -687,10 +682,10 @@ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
         */
 
        /* Disable all L1 substates */
-       pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
-                               PCI_L1SS_CTL1_L1SS_MASK, 0);
-       pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
-                               PCI_L1SS_CTL1_L1SS_MASK, 0);
+       pci_clear_and_set_config_dword(child, child->l1ss + PCI_L1SS_CTL1,
+                                      PCI_L1SS_CTL1_L1SS_MASK, 0);
+       pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
+                                      PCI_L1SS_CTL1_L1SS_MASK, 0);
        /*
         * If needed, disable L1, and it gets enabled later
         * in pcie_config_aspm_link().
@@ -713,10 +708,10 @@ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
                val |= PCI_L1SS_CTL1_PCIPM_L1_2;
 
        /* Enable what we need to enable */
-       pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
-                               PCI_L1SS_CTL1_L1SS_MASK, val);
-       pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
-                               PCI_L1SS_CTL1_L1SS_MASK, val);
+       pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
+                                      PCI_L1SS_CTL1_L1SS_MASK, val);
+       pci_clear_and_set_config_dword(child, child->l1ss + PCI_L1SS_CTL1,
+                                      PCI_L1SS_CTL1_L1SS_MASK, val);
 }
 
 static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)

diff --git a/include/linux/pci.h b/include/linux/pci.h
index 60ca768bc8679f4ff135f2d0364e46b5e7ab4fb9..268c4bd98ef3e6e88a50fe4886857c0f1b147219 100644 (file)
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -1239,6 +1239,8 @@ int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
+void pci_clear_and_set_config_dword(const struct pci_dev *dev, int pos,
+                                   u32 clear, u32 set);
 
 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);