scsi: ufs: ufs-mediatek: Change dbg select by check IP version

Mediatek UFS dbg select setting is changed in new IP version.  Check the IP
version before setting dbg select.

Link: https://lore.kernel.org/r/1630918387-8333-1-git-send-email-peter.wang@mediatek.com
Signed-off-by: Peter Wang <peter.wang@mediatek.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>

diff --git a/drivers/scsi/ufs/ufs-mediatek.c b/drivers/scsi/ufs/ufs-mediatek.c
index 80b3545dd17d64af8f4891ca65893cd5548a895c..d2d7e76c5ec85d098619b5ecc869dfe1bd3d4cfd 100644 (file)
--- a/drivers/scsi/ufs/ufs-mediatek.c
+++ b/drivers/scsi/ufs/ufs-mediatek.c
@@ -296,6 +296,21 @@ static void ufs_mtk_setup_ref_clk_wait_us(struct ufs_hba *hba,
        host->ref_clk_ungating_wait_us = ungating_us;
 }
 
+static void ufs_mtk_dbg_sel(struct ufs_hba *hba)
+{
+       struct ufs_mtk_host *host = ufshcd_get_variant(hba);
+
+       if (((host->ip_ver >> 16) & 0xFF) >= 0x36) {
+               ufshcd_writel(hba, 0x820820, REG_UFS_DEBUG_SEL);
+               ufshcd_writel(hba, 0x0, REG_UFS_DEBUG_SEL_B0);
+               ufshcd_writel(hba, 0x55555555, REG_UFS_DEBUG_SEL_B1);
+               ufshcd_writel(hba, 0xaaaaaaaa, REG_UFS_DEBUG_SEL_B2);
+               ufshcd_writel(hba, 0xffffffff, REG_UFS_DEBUG_SEL_B3);
+       } else {
+               ufshcd_writel(hba, 0x20, REG_UFS_DEBUG_SEL);
+       }
+}
+
 static int ufs_mtk_wait_link_state(struct ufs_hba *hba, u32 state,
                                   unsigned long max_wait_ms)
 {
@@ -305,7 +320,7 @@ static int ufs_mtk_wait_link_state(struct ufs_hba *hba, u32 state,
        timeout = ktime_add_ms(ktime_get(), max_wait_ms);
        do {
                time_checked = ktime_get();
-               ufshcd_writel(hba, 0x20, REG_UFS_DEBUG_SEL);
+               ufs_mtk_dbg_sel(hba);
                val = ufshcd_readl(hba, REG_UFS_PROBE);
                val = val >> 28;
 
@@ -689,6 +704,8 @@ static int ufs_mtk_init(struct ufs_hba *hba)
        ufs_mtk_mphy_power_on(hba, true);
        ufs_mtk_setup_clocks(hba, true, POST_CHANGE);
 
+       host->ip_ver = ufshcd_readl(hba, REG_UFS_MTK_IP_VER);
+
        goto out;
 
 out_variant_clear:
@@ -1001,7 +1018,7 @@ static void ufs_mtk_dbg_register_dump(struct ufs_hba *hba)
                         "MPHY Ctrl ");
 
        /* Direct debugging information to REG_MTK_PROBE */
-       ufshcd_writel(hba, 0x20, REG_UFS_DEBUG_SEL);
+       ufs_mtk_dbg_sel(hba);
        ufshcd_dump_regs(hba, REG_UFS_PROBE, 0x4, "Debug Probe ");
 }
 

diff --git a/drivers/scsi/ufs/ufs-mediatek.h b/drivers/scsi/ufs/ufs-mediatek.h
index 3f0d3bb769e89b4a4a2543e952580f59e30cf215..524c8e2c1e6ffd3dc1ad8005ae2522a666b6bdb4 100644 (file)
--- a/drivers/scsi/ufs/ufs-mediatek.h
+++ b/drivers/scsi/ufs/ufs-mediatek.h
@@ -15,9 +15,14 @@
 #define REG_UFS_REFCLK_CTRL         0x144
 #define REG_UFS_EXTREG              0x2100
 #define REG_UFS_MPHYCTRL            0x2200
+#define REG_UFS_MTK_IP_VER          0x2240
 #define REG_UFS_REJECT_MON          0x22AC
 #define REG_UFS_DEBUG_SEL           0x22C0
 #define REG_UFS_PROBE               0x22C8
+#define REG_UFS_DEBUG_SEL_B0        0x22D0
+#define REG_UFS_DEBUG_SEL_B1        0x22D4
+#define REG_UFS_DEBUG_SEL_B2        0x22D8
+#define REG_UFS_DEBUG_SEL_B3        0x22DC
 
 /*
  * Ref-clk control
@@ -113,6 +118,7 @@ struct ufs_mtk_host {
        bool ref_clk_enabled;
        u16 ref_clk_ungating_wait_us;
        u16 ref_clk_gating_wait_us;
+       u32 ip_ver;
 };
 
 #endif /* !_UFS_MEDIATEK_H */