PCI: dw-rockchip: Describe Resizable BARs as Resizable BARs

Looking at section "11.4.4.29 USP_PCIE_RESBAR Registers Summary" in the
Technical Reference Manual (TRM) for RK3588, we can see that none of the
BARs are Fixed BARs, but actually Resizable BARs.

I couldn't find any reference in the TRM for RK3568, but looking at the
downstream PCIe endpoint driver, both RK3568 and RK3588 are treated as
the same, so the BARs on RK3568 must also be Resizable BARs.

Now when we actually have support for Resizable BARs, let's configure
these BARs as such.

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Link: https://lore.kernel.org/r/20250131182949.465530-16-cassel@kernel.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>

diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
index 93698abff4d9c7694822f33acb5f598240918ac5..df2eaa35d0450e2a9b5f5b7301e2c84691e3d70d 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
@@ -273,12 +273,12 @@ static const struct pci_epc_features rockchip_pcie_epc_features_rk3568 = {
        .msi_capable = true,
        .msix_capable = true,
        .align = SZ_64K,
-       .bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
-       .bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
-       .bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
-       .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
-       .bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
-       .bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
+       .bar[BAR_0] = { .type = BAR_RESIZABLE, },
+       .bar[BAR_1] = { .type = BAR_RESIZABLE, },
+       .bar[BAR_2] = { .type = BAR_RESIZABLE, },
+       .bar[BAR_3] = { .type = BAR_RESIZABLE, },
+       .bar[BAR_4] = { .type = BAR_RESIZABLE, },
+       .bar[BAR_5] = { .type = BAR_RESIZABLE, },
 };
 
 /*
@@ -293,12 +293,12 @@ static const struct pci_epc_features rockchip_pcie_epc_features_rk3588 = {
        .msi_capable = true,
        .msix_capable = true,
        .align = SZ_64K,
-       .bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
-       .bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
-       .bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
-       .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
+       .bar[BAR_0] = { .type = BAR_RESIZABLE, },
+       .bar[BAR_1] = { .type = BAR_RESIZABLE, },
+       .bar[BAR_2] = { .type = BAR_RESIZABLE, },
+       .bar[BAR_3] = { .type = BAR_RESIZABLE, },
        .bar[BAR_4] = { .type = BAR_RESERVED, },
-       .bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
+       .bar[BAR_5] = { .type = BAR_RESIZABLE, },
 };
 
 static const struct pci_epc_features *