net/mlx5: Query ADV_RDMA capabilities

Query ADV_RDMA capabilities which provide information for
advanced RDMA related features.

Signed-off-by: Patrisious Haddad <phaddad@nvidia.com>
Reviewed-by: Mark Bloch <mbloch@nvidia.com>
Link: https://patch.msgid.link/e3e6ede03ea31cd201078dcdd4e407608e4a5a87.1740574103.git.leon@kernel.org
Signed-off-by: Leon Romanovsky <leon@kernel.org>

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fw.c b/drivers/net/ethernet/mellanox/mlx5/core/fw.c
index b253d1673398dc393df5c3b0139cdba31c754607..57476487e31fe5eba73ed101ac36f8aac876e4b4 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/fw.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/fw.c
@@ -287,6 +287,13 @@ int mlx5_query_hca_caps(struct mlx5_core_dev *dev)
                        return err;
        }
 
+       if (MLX5_CAP_GEN(dev, adv_rdma)) {
+               err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ADV_RDMA,
+                                             HCA_CAP_OPMOD_GET_CUR);
+               if (err)
+                       return err;
+       }
+
        return 0;
 }
 

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/ethernet/mellanox/mlx5/core/main.c
index ec956c4bcebdbaf2546862d072b7844b177de243..af0b677393d0862b7abdec843f9b6ba43f0c766b 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/main.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c
@@ -1795,6 +1795,7 @@ static const int types[] = {
        MLX5_CAP_ADV_VIRTUALIZATION,
        MLX5_CAP_CRYPTO,
        MLX5_CAP_SHAMPO,
+       MLX5_CAP_ADV_RDMA,
 };
 
 static void mlx5_hca_caps_free(struct mlx5_core_dev *dev)

diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h
index fd37f4e54d7610b27e0e0a22d8ed3358d206a7a7..0ae6d69c5221d51634b0ac4b4dbf3e4356c06163 100644 (file)
--- a/include/linux/mlx5/device.h
+++ b/include/linux/mlx5/device.h
@@ -1251,6 +1251,7 @@ enum mlx5_cap_type {
        MLX5_CAP_GENERAL_2 = 0x20,
        MLX5_CAP_PORT_SELECTION = 0x25,
        MLX5_CAP_ADV_VIRTUALIZATION = 0x26,
+       MLX5_CAP_ADV_RDMA = 0x28,
        /* NUM OF CAP Types */
        MLX5_CAP_NUM
 };
@@ -1384,6 +1385,10 @@ enum mlx5_qcam_feature_groups {
        MLX5_GET(adv_virtualization_cap, \
                 mdev->caps.hca[MLX5_CAP_ADV_VIRTUALIZATION]->cur, cap)
 
+#define MLX5_CAP_ADV_RDMA(mdev, cap) \
+       MLX5_GET(adv_rdma_cap, \
+                mdev->caps.hca[MLX5_CAP_ADV_RDMA]->cur, cap)
+
 #define MLX5_CAP_FLOWTABLE_PORT_SELECTION(mdev, cap) \
        MLX5_CAP_PORT_SELECTION(mdev, flow_table_properties_port_selection.cap)
 

diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index 3b3d88ffcacc6792a8e3f40871fbd0d12a5b0907..fea8af42f95480b2833c71d1dccbb72dbe17ada2 100644 (file)
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -1993,7 +1993,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8         max_geneve_tlv_options[0x8];
        u8         reserved_at_568[0x3];
        u8         max_geneve_tlv_option_data_len[0x5];
-       u8         reserved_at_570[0x9];
+       u8         reserved_at_570[0x1];
+       u8         adv_rdma[0x1];
+       u8         reserved_at_572[0x7];
        u8         adv_virtualization[0x1];
        u8         reserved_at_57a[0x6];
 
@@ -13076,6 +13078,44 @@ struct mlx5_ifc_load_vhca_state_out_bits {
        u8         reserved_at_40[0x40];
 };
 
+struct mlx5_ifc_adv_rdma_cap_bits {
+       u8         rdma_transport_manager[0x1];
+       u8         rdma_transport_manager_other_eswitch[0x1];
+       u8         reserved_at_2[0x1e];
+
+       u8         rcx_type[0x8];
+       u8         reserved_at_28[0x2];
+       u8         ps_entry_log_max_value[0x6];
+       u8         reserved_at_30[0x6];
+       u8         qp_max_ps_num_entry[0xa];
+
+       u8         mp_max_num_queues[0x8];
+       u8         ps_user_context_max_log_size[0x8];
+       u8         message_based_qp_and_striding_wq[0x8];
+       u8         reserved_at_58[0x8];
+
+       u8         max_receive_send_message_size_stride[0x10];
+       u8         reserved_at_70[0x10];
+
+       u8         max_receive_send_message_size_byte[0x20];
+
+       u8         reserved_at_a0[0x160];
+
+       struct mlx5_ifc_flow_table_prop_layout_bits rdma_transport_rx_flow_table_properties;
+
+       struct mlx5_ifc_flow_table_prop_layout_bits rdma_transport_tx_flow_table_properties;
+
+       struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_rx_ft_field_support_2;
+
+       struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_tx_ft_field_support_2;
+
+       struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_rx_ft_field_bitmask_support_2;
+
+       struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_tx_ft_field_bitmask_support_2;
+
+       u8         reserved_at_800[0x3800];
+};
+
 struct mlx5_ifc_adv_virtualization_cap_bits {
        u8         reserved_at_0[0x3];
        u8         pg_track_log_max_num[0x5];