ARM: dts: r8a7745: Add APMU node and second CPU core

Add DT node for the Advanced Power Management Unit (APMU), add the
second CPU core, and use "renesas,apmu" as "enable-method".

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index de13e156f071147a78a84a77ad2f02ddbc981850..0fa78612746f586ab3aecaac1e0298066521466a 100644 (file)
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -38,6 +38,7 @@
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
+               enable-method = "renesas,apmu";
 
                cpu0: cpu@0 {
                        device_type = "cpu";
@@ -49,6 +50,15 @@
                        next-level-cache = <&L2_CA7>;
                };
 
+               cpu1: cpu@1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a7";
+                       reg = <1>;
+                       clock-frequency = <1000000000>;
+                       power-domains = <&sysc R8A7745_PD_CA7_CPU1>;
+                       next-level-cache = <&L2_CA7>;
+               };
+
                L2_CA7: cache-controller-0 {
                        compatible = "cache";
                        cache-unified;
@@ -65,6 +75,12 @@
                #size-cells = <2>;
                ranges;
 
+               apmu@e6151000 {
+                       compatible = "renesas,r8a7745-apmu", "renesas,apmu";
+                       reg = <0 0xe6151000 0 0x188>;
+                       cpus = <&cpu0 &cpu1>;
+               };
+
                gic: interrupt-controller@f1001000 {
                        compatible = "arm,gic-400";
                        #interrupt-cells = <3>;