PCI: dwc: Make use of GENMASK/FIELD_PREP

Convert various multi-bit fields to be defined using GENMASK/FIELD_PREP.
This way bit field boundaries are defined in a single place only, as
well as defined in a way that makes it easier to verify them against the
reference manual. No functional change intended.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: "A.s. Dong" <aisheng.dong@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: linux-imx@nxp.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org

diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 070382869685a83e99f113e0668b044775724046..8ebfb06584d9010a3529ca186b852ee87d4eaeea 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -11,6 +11,7 @@
 #ifndef _PCIE_DESIGNWARE_H
 #define _PCIE_DESIGNWARE_H
 
+#include <linux/bitfield.h>
 #include <linux/dma-mapping.h>
 #include <linux/irq.h>
 #include <linux/msi.h>
@@ -30,11 +31,12 @@
 
 /* Synopsys-specific PCIe configuration registers */
 #define PCIE_PORT_LINK_CONTROL         0x710
-#define PORT_LINK_MODE_MASK            (0x3f << 16)
-#define PORT_LINK_MODE_1_LANES         (0x1 << 16)
-#define PORT_LINK_MODE_2_LANES         (0x3 << 16)
-#define PORT_LINK_MODE_4_LANES         (0x7 << 16)
-#define PORT_LINK_MODE_8_LANES         (0xf << 16)
+#define PORT_LINK_MODE_MASK            GENMASK(21, 16)
+#define PORT_LINK_MODE(n)              FIELD_PREP(PORT_LINK_MODE_MASK, n)
+#define PORT_LINK_MODE_1_LANES         PORT_LINK_MODE(0x1)
+#define PORT_LINK_MODE_2_LANES         PORT_LINK_MODE(0x3)
+#define PORT_LINK_MODE_4_LANES         PORT_LINK_MODE(0x7)
+#define PORT_LINK_MODE_8_LANES         PORT_LINK_MODE(0xf)
 
 #define PCIE_PORT_DEBUG0               0x728
 #define PORT_LOGIC_LTSSM_STATE_MASK    0x1f
@@ -42,11 +44,12 @@
 
 #define PCIE_LINK_WIDTH_SPEED_CONTROL  0x80C
 #define PORT_LOGIC_SPEED_CHANGE                BIT(17)
-#define PORT_LOGIC_LINK_WIDTH_MASK     (0x1f << 8)
-#define PORT_LOGIC_LINK_WIDTH_1_LANES  (0x1 << 8)
-#define PORT_LOGIC_LINK_WIDTH_2_LANES  (0x2 << 8)
-#define PORT_LOGIC_LINK_WIDTH_4_LANES  (0x4 << 8)
-#define PORT_LOGIC_LINK_WIDTH_8_LANES  (0x8 << 8)
+#define PORT_LOGIC_LINK_WIDTH_MASK     GENMASK(12, 8)
+#define PORT_LOGIC_LINK_WIDTH(n)       FIELD_PREP(PORT_LOGIC_LINK_WIDTH_MASK, n)
+#define PORT_LOGIC_LINK_WIDTH_1_LANES  PORT_LOGIC_LINK_WIDTH(0x1)
+#define PORT_LOGIC_LINK_WIDTH_2_LANES  PORT_LOGIC_LINK_WIDTH(0x2)
+#define PORT_LOGIC_LINK_WIDTH_4_LANES  PORT_LOGIC_LINK_WIDTH(0x4)
+#define PORT_LOGIC_LINK_WIDTH_8_LANES  PORT_LOGIC_LINK_WIDTH(0x8)
 
 #define PCIE_MSI_ADDR_LO               0x820
 #define PCIE_MSI_ADDR_HI               0x824
@@ -72,9 +75,9 @@
 #define PCIE_ATU_UPPER_BASE            0x910
 #define PCIE_ATU_LIMIT                 0x914
 #define PCIE_ATU_LOWER_TARGET          0x918
-#define PCIE_ATU_BUS(x)                        (((x) & 0xff) << 24)
-#define PCIE_ATU_DEV(x)                        (((x) & 0x1f) << 19)
-#define PCIE_ATU_FUNC(x)               (((x) & 0x7) << 16)
+#define PCIE_ATU_BUS(x)                        FIELD_PREP(GENMASK(31, 24), x)
+#define PCIE_ATU_DEV(x)                        FIELD_PREP(GENMASK(23, 19), x)
+#define PCIE_ATU_FUNC(x)               FIELD_PREP(GENMASK(18, 16), x)
 #define PCIE_ATU_UPPER_TARGET          0x91C
 
 #define PCIE_MISC_CONTROL_1_OFF                0x8BC