drm/amd/display: Use sync version of indirect register access.

[Why]
Access to indirect registers by DC and other components are not synchronized.

[How]
Use sync version of indirect register access.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: JinZe.Xu <JinZe.Xu@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
index 2d14346b680e36afaed5af925e6e0c8de4c4dd1c..478b4d6a354405231751707959d517b98f3eae30 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
@@ -49,12 +49,9 @@ static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E0000
                                        { { 0, 0, 0, 0, 0, 0 } },
                                        { { 0, 0, 0, 0, 0, 0 } },
                                        { { 0, 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
-                                       { { 0, 0, 0, 0, 0, 0 } },
-                                       { { 0, 0, 0, 0, 0, 0 } },
-                                       { { 0, 0, 0, 0, 0, 0 } },
-                                       { { 0, 0, 0, 0, 0, 0 } },
-                                       { { 0, 0, 0, 0, 0, 0 } } } };
+
+#define CTX clk_mgr->base.ctx
+#define IND_REG(offset)        offset
 
 #define regBIF_BX_PF2_RSMU_INDEX                                                                        0x0000
 #define regBIF_BX_PF2_RSMU_INDEX_BASE_IDX                                                               1
@@ -67,9 +64,6 @@ static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D
 #define FN(reg_name, field) \
        FD(reg_name##__##field)
 
-#define REG_NBIO(reg_name) \
-       (NBIO_BASE.instance[0].segment[regBIF_BX_PF2_ ## reg_name ## _BASE_IDX] + regBIF_BX_PF2_ ## reg_name)
-
 #undef DC_LOGGER
 #define DC_LOGGER \
        CTX->logger
@@ -77,6 +71,13 @@ static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D
 
 #define mmMP1_C2PMSG_3                            0x3B1050C
 
+#define reg__MP1_C2PMSG_3_MASK                                 (0xFFFFFFFF)
+#define reg__MP1_C2PMSG_3__SHIFT                                       (0)
+
+
+#define data_reg_name__MP1_C2PMSG_3_MASK               (0xFFFFFFFF)
+#define data_reg_name__MP1_C2PMSG_3__SHIFT             (0)
+
 #define VBIOSSMC_MSG_TestMessage                  0x01 ///< To check if PMFW is alive and responding. Requirement specified by PMFW team
 #define VBIOSSMC_MSG_GetPmfwVersion               0x02 ///< Get PMFW version
 #define VBIOSSMC_MSG_Spare0                       0x03 ///< Spare0
@@ -153,12 +154,10 @@ static int dcn315_smu_send_msg_with_param(
 
        for (i = 0; i < SMU_REGISTER_WRITE_RETRY_COUNT; i++) {
                /* Trigger the message transaction by writing the message ID */
-               generic_write_indirect_reg(CTX,
-                       REG_NBIO(RSMU_INDEX), REG_NBIO(RSMU_DATA),
-                       mmMP1_C2PMSG_3, msg_id);
-               read_back_data = generic_read_indirect_reg(CTX,
-                       REG_NBIO(RSMU_INDEX), REG_NBIO(RSMU_DATA),
-                       mmMP1_C2PMSG_3);
+               IX_REG_SET_SYNC(mmMP1_C2PMSG_3, 0,
+                       MP1_C2PMSG_3, msg_id);
+               IX_REG_GET_SYNC(mmMP1_C2PMSG_3,
+                       MP1_C2PMSG_3, &read_back_data);
                if (read_back_data == msg_id)
                        break;
                udelay(2);

diff --git a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
index a402df225a76e9d0bb4408c5fd843041542f5306..26cb1459b743fcd6dde1aa24ddb1d17d73f8fb03 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
@@ -508,6 +508,10 @@ uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx,
                                initial_val, \
                                n, __VA_ARGS__)
 
+#define IX_REG_SET_SYNC(index, init_value, f1, v1)     \
+               IX_REG_SET_N_SYNC(index, 1, init_value, \
+                               FN(reg, f1), v1)
+
 #define IX_REG_SET_2_SYNC(index, init_value, f1, v1, f2, v2)   \
                IX_REG_SET_N_SYNC(index, 2, init_value, \
                                FN(reg, f1), v1,\