MIPS: Convert MIPS34K_MISSED_ITLB_WAR into a config option

Use a new config option to enable MIPS 34K ITLB workaround and remove
define from different war.h files.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 87ef000d1aecc2e0cf3fd8c7023d7ee76950e113..632fe8fe68c4846ca8eccf9aae33fea99cc86cb4 100644 (file)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2683,6 +2683,10 @@ config WAR_ICACHE_REFILLS
 config WAR_R10000_LLSC
        bool
 
+# 34K core erratum: "Problems Executing the TLBR Instruction"
+config WAR_MIPS34K_MISSED_ITLB
+       bool
+
 #
 # - Highmem only makes sense for the 32-bit kernel.
 # - The current highmem code will only work properly on physically indexed

diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h
index 52be3785e3e21a23328e6ba1fe0cff7fc7e88e87..9aa4ea5522a9013a2ccc3c5c5c5d250b7f74c3a6 100644 (file)
--- a/arch/mips/include/asm/mach-cavium-octeon/war.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/war.h
@@ -11,7 +11,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define MIPS34K_MISSED_ITLB_WAR                0
 
 #define CAVIUM_OCTEON_DCACHE_PREFETCH_WAR      \
        OCTEON_IS_MODEL(OCTEON_CN6XXX)

diff --git a/arch/mips/include/asm/mach-generic/war.h b/arch/mips/include/asm/mach-generic/war.h
index 2229c83772889e70c26908806fbb2ddf8488d3bc..4f25636661d5b5f71ac38204e8335cd6442d2bf7 100644 (file)
--- a/arch/mips/include/asm/mach-generic/war.h
+++ b/arch/mips/include/asm/mach-generic/war.h
@@ -10,6 +10,5 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define MIPS34K_MISSED_ITLB_WAR                0
 
 #endif /* __ASM_MACH_GENERIC_WAR_H */

diff --git a/arch/mips/include/asm/mach-ip22/war.h b/arch/mips/include/asm/mach-ip22/war.h
index f10efe589f93e74f7ef47d046bee5ed28a5cba29..09169cfbf932fba9f61e384de72dd13a0026c021 100644 (file)
--- a/arch/mips/include/asm/mach-ip22/war.h
+++ b/arch/mips/include/asm/mach-ip22/war.h
@@ -10,6 +10,5 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define MIPS34K_MISSED_ITLB_WAR                0
 
 #endif /* __ASM_MIPS_MACH_IP22_WAR_H */

diff --git a/arch/mips/include/asm/mach-ip27/war.h b/arch/mips/include/asm/mach-ip27/war.h
index 0a07cf6731c0d5ecfa261c2dd3fe958bb4b0962c..1c81d5464235d4b3365b37b0c2184ef1732dbcc8 100644 (file)
--- a/arch/mips/include/asm/mach-ip27/war.h
+++ b/arch/mips/include/asm/mach-ip27/war.h
@@ -10,6 +10,5 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define MIPS34K_MISSED_ITLB_WAR                0
 
 #endif /* __ASM_MIPS_MACH_IP27_WAR_H */

diff --git a/arch/mips/include/asm/mach-ip28/war.h b/arch/mips/include/asm/mach-ip28/war.h
index 9fdc6425c22c00cba7387dc98c8b0dd7c2bddfe9..ff66adbaaae58c5ea7218d37467cf4ad1955bf48 100644 (file)
--- a/arch/mips/include/asm/mach-ip28/war.h
+++ b/arch/mips/include/asm/mach-ip28/war.h
@@ -10,6 +10,5 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define MIPS34K_MISSED_ITLB_WAR                0
 
 #endif /* __ASM_MIPS_MACH_IP28_WAR_H */

diff --git a/arch/mips/include/asm/mach-ip30/war.h b/arch/mips/include/asm/mach-ip30/war.h
index 8a8ec55780834f982e96473f00f16de762d2a52f..b00469a398351e38f2520446cc42b6e1b7d339ec 100644 (file)
--- a/arch/mips/include/asm/mach-ip30/war.h
+++ b/arch/mips/include/asm/mach-ip30/war.h
@@ -7,6 +7,5 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define MIPS34K_MISSED_ITLB_WAR                0
 
 #endif /* __ASM_MIPS_MACH_IP30_WAR_H */

diff --git a/arch/mips/include/asm/mach-ip32/war.h b/arch/mips/include/asm/mach-ip32/war.h
index 9e8c0c2a4c265fce11b00066ec385fa2d624c98b..c57a9cd2e50b80ad513b8a17859e12e11d0f1040 100644 (file)
--- a/arch/mips/include/asm/mach-ip32/war.h
+++ b/arch/mips/include/asm/mach-ip32/war.h
@@ -10,6 +10,5 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define MIPS34K_MISSED_ITLB_WAR                0
 
 #endif /* __ASM_MIPS_MACH_IP32_WAR_H */

diff --git a/arch/mips/include/asm/mach-malta/war.h b/arch/mips/include/asm/mach-malta/war.h
index 76f7de21b7dd7e3e4ddd272911a9a76e6853a786..73c9e6d84a8f05d9d163c78f0c8daf0f401f1827 100644 (file)
--- a/arch/mips/include/asm/mach-malta/war.h
+++ b/arch/mips/include/asm/mach-malta/war.h
@@ -10,6 +10,5 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define MIPS34K_MISSED_ITLB_WAR                0
 
 #endif /* __ASM_MIPS_MACH_MIPS_WAR_H */

diff --git a/arch/mips/include/asm/mach-rc32434/war.h b/arch/mips/include/asm/mach-rc32434/war.h
index 76f7de21b7dd7e3e4ddd272911a9a76e6853a786..73c9e6d84a8f05d9d163c78f0c8daf0f401f1827 100644 (file)
--- a/arch/mips/include/asm/mach-rc32434/war.h
+++ b/arch/mips/include/asm/mach-rc32434/war.h
@@ -10,6 +10,5 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define MIPS34K_MISSED_ITLB_WAR                0
 
 #endif /* __ASM_MIPS_MACH_MIPS_WAR_H */

diff --git a/arch/mips/include/asm/mach-rm/war.h b/arch/mips/include/asm/mach-rm/war.h
index dcb80b558321c9b1ed8fb03b9efe87e81e624c19..c396a31706ac71d7ee25a2989f9ca5ea3bd7be7c 100644 (file)
--- a/arch/mips/include/asm/mach-rm/war.h
+++ b/arch/mips/include/asm/mach-rm/war.h
@@ -10,6 +10,5 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define MIPS34K_MISSED_ITLB_WAR                0
 
 #endif /* __ASM_MIPS_MACH_RM_WAR_H */

diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h
index 0cf25eea846f014b89cb502236d012938cf7e0be..fa9bbc228dd72731703c61052921cf68c53fe78d 100644 (file)
--- a/arch/mips/include/asm/mach-sibyte/war.h
+++ b/arch/mips/include/asm/mach-sibyte/war.h
@@ -24,6 +24,4 @@ extern int sb1250_m3_workaround_needed(void);
 
 #endif
 
-#define MIPS34K_MISSED_ITLB_WAR                0
-
 #endif /* __ASM_MIPS_MACH_SIBYTE_WAR_H */

diff --git a/arch/mips/include/asm/mach-tx49xx/war.h b/arch/mips/include/asm/mach-tx49xx/war.h
index 8e572d7d2b6ec064eaf25938c5e5f5d026ad290c..7213d9334f3f1f4f32b69f179daca5da92f86a28 100644 (file)
--- a/arch/mips/include/asm/mach-tx49xx/war.h
+++ b/arch/mips/include/asm/mach-tx49xx/war.h
@@ -10,6 +10,5 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define MIPS34K_MISSED_ITLB_WAR                0
 
 #endif /* __ASM_MIPS_MACH_TX49XX_WAR_H */

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 1a03fdc2c74a9703403f8a2e862cc9dcc56ac0a7..3a7379b8f31cd589dfaad3bf5bd7dd8cb1a0f0dd 100644 (file)
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -2716,7 +2716,7 @@ static inline void tlb_probe(void)
 
 static inline void tlb_read(void)
 {
-#if MIPS34K_MISSED_ITLB_WAR
+#ifdef CONFIG_WAR_MIPS34K_MISSED_ITLB
        int res = 0;
 
        __asm__ __volatile__(
@@ -2738,7 +2738,7 @@ static inline void tlb_read(void)
                "tlbr\n\t"
                ".set reorder");
 
-#if MIPS34K_MISSED_ITLB_WAR
+#ifdef CONFIG_WAR_MIPS34K_MISSED_ITLB
        if ((res & _ULCAST_(1)))
                __asm__ __volatile__(
                "       .set    push                            \n"

diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h
index d405ecb78cbdd064b46bb9bf258ff38804c1a769..4f4d37b3dd074ea67845bab390b55a0519d4b407 100644 (file)
--- a/arch/mips/include/asm/war.h
+++ b/arch/mips/include/asm/war.h
@@ -93,11 +93,4 @@
 #error Check setting of SIBYTE_1956_WAR for your platform
 #endif
 
-/*
- * 34K core erratum: "Problems Executing the TLBR Instruction"
- */
-#ifndef MIPS34K_MISSED_ITLB_WAR
-#error Check setting of MIPS34K_MISSED_ITLB_WAR for your platform
-#endif
-
 #endif /* _ASM_WAR_H */