octeontx2-af: Disable backpressure between CPT and NIX

NIX can assert backpressure to CPT on the NIX<=>CPT link.
Keep the backpressure disabled for now. NIX block anyways
handles backpressure asserted by MAC due to PFC or flow
control pkts.

Signed-off-by: Bharat Bhushan <bbhushan2@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
index 62c07407eb941997b39ba1cd4a4208a348e75c52..005ca8a056c0afbceea919b0534a72d042426f0e 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
@@ -313,6 +313,10 @@ M(NIX_BANDPROF_FREE,       0x801e, nix_bandprof_free, nix_bandprof_free_req,   \
                                msg_rsp)                                    \
 M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req,           \
                                nix_bandprof_get_hwinfo_rsp)                \
+M(NIX_CPT_BP_ENABLE,    0x8020, nix_cpt_bp_enable, nix_bp_cfg_req,         \
+                               nix_bp_cfg_rsp)                             \
+M(NIX_CPT_BP_DISABLE,   0x8021, nix_cpt_bp_disable, nix_bp_cfg_req,        \
+                               msg_rsp)                                \
 M(NIX_READ_INLINE_IPSEC_CFG, 0x8023, nix_read_inline_ipsec_cfg,                \
                                msg_req, nix_inline_ipsec_cfg)          \
 M(NIX_MCAST_GRP_CREATE,        0x802b, nix_mcast_grp_create, nix_mcast_grp_create_req, \

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
index a5d1e2bddd58db8966a1a59b43d777e6f011db3c..613655fcd34f481219befca6c922fa7ab30a467b 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
@@ -569,9 +569,17 @@ void rvu_nix_flr_free_bpids(struct rvu *rvu, u16 pcifunc)
        mutex_unlock(&rvu->rsrc_lock);
 }
 
-int rvu_mbox_handler_nix_bp_disable(struct rvu *rvu,
-                                   struct nix_bp_cfg_req *req,
-                                   struct msg_rsp *rsp)
+static u16 nix_get_channel(u16 chan, bool cpt_link)
+{
+       /* CPT channel for a given link channel is always
+        * assumed to be BIT(11) set in link channel.
+        */
+       return cpt_link ? chan | BIT(11) : chan;
+}
+
+static int nix_bp_disable(struct rvu *rvu,
+                         struct nix_bp_cfg_req *req,
+                         struct msg_rsp *rsp, bool cpt_link)
 {
        u16 pcifunc = req->hdr.pcifunc;
        int blkaddr, pf, type, err;
@@ -579,6 +587,7 @@ int rvu_mbox_handler_nix_bp_disable(struct rvu *rvu,
        struct rvu_pfvf *pfvf;
        struct nix_hw *nix_hw;
        struct nix_bp *bp;
+       u16 chan_v;
        u64 cfg;
 
        pf = rvu_get_pf(pcifunc);
@@ -589,6 +598,9 @@ int rvu_mbox_handler_nix_bp_disable(struct rvu *rvu,
        if (is_sdp_pfvf(pcifunc))
                type = NIX_INTF_TYPE_SDP;
 
+       if (cpt_link && !rvu->hw->cpt_links)
+               return 0;
+
        pfvf = rvu_get_pfvf(rvu, pcifunc);
        err = nix_get_struct_ptrs(rvu, pcifunc, &nix_hw, &blkaddr);
        if (err)
@@ -597,8 +609,9 @@ int rvu_mbox_handler_nix_bp_disable(struct rvu *rvu,
        bp = &nix_hw->bp;
        chan_base = pfvf->rx_chan_base + req->chan_base;
        for (chan = chan_base; chan < (chan_base + req->chan_cnt); chan++) {
-               cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan));
-               rvu_write64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan),
+               chan_v = nix_get_channel(chan, cpt_link);
+               cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan_v));
+               rvu_write64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan_v),
                            cfg & ~BIT_ULL(16));
 
                if (type == NIX_INTF_TYPE_LBK) {
@@ -617,6 +630,20 @@ int rvu_mbox_handler_nix_bp_disable(struct rvu *rvu,
        return 0;
 }
 
+int rvu_mbox_handler_nix_bp_disable(struct rvu *rvu,
+                                   struct nix_bp_cfg_req *req,
+                                   struct msg_rsp *rsp)
+{
+       return nix_bp_disable(rvu, req, rsp, false);
+}
+
+int rvu_mbox_handler_nix_cpt_bp_disable(struct rvu *rvu,
+                                       struct nix_bp_cfg_req *req,
+                                       struct msg_rsp *rsp)
+{
+       return nix_bp_disable(rvu, req, rsp, true);
+}
+
 static int rvu_nix_get_bpid(struct rvu *rvu, struct nix_bp_cfg_req *req,
                            int type, int chan_id)
 {
@@ -696,15 +723,17 @@ static int rvu_nix_get_bpid(struct rvu *rvu, struct nix_bp_cfg_req *req,
        return bpid;
 }
 
-int rvu_mbox_handler_nix_bp_enable(struct rvu *rvu,
-                                  struct nix_bp_cfg_req *req,
-                                  struct nix_bp_cfg_rsp *rsp)
+static int nix_bp_enable(struct rvu *rvu,
+                        struct nix_bp_cfg_req *req,
+                        struct nix_bp_cfg_rsp *rsp,
+                        bool cpt_link)
 {
        int blkaddr, pf, type, chan_id = 0;
        u16 pcifunc = req->hdr.pcifunc;
        struct rvu_pfvf *pfvf;
        u16 chan_base, chan;
        s16 bpid, bpid_base;
+       u16 chan_v;
        u64 cfg;
 
        pf = rvu_get_pf(pcifunc);
@@ -717,6 +746,9 @@ int rvu_mbox_handler_nix_bp_enable(struct rvu *rvu,
            type != NIX_INTF_TYPE_SDP)
                return 0;
 
+       if (cpt_link && !rvu->hw->cpt_links)
+               return 0;
+
        pfvf = rvu_get_pfvf(rvu, pcifunc);
        blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
 
@@ -730,9 +762,11 @@ int rvu_mbox_handler_nix_bp_enable(struct rvu *rvu,
                        return -EINVAL;
                }
 
-               cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan));
+               chan_v = nix_get_channel(chan, cpt_link);
+
+               cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan_v));
                cfg &= ~GENMASK_ULL(8, 0);
-               rvu_write64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan),
+               rvu_write64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan_v),
                            cfg | (bpid & GENMASK_ULL(8, 0)) | BIT_ULL(16));
                chan_id++;
                bpid = rvu_nix_get_bpid(rvu, req, type, chan_id);
@@ -750,6 +784,20 @@ int rvu_mbox_handler_nix_bp_enable(struct rvu *rvu,
        return 0;
 }
 
+int rvu_mbox_handler_nix_bp_enable(struct rvu *rvu,
+                                  struct nix_bp_cfg_req *req,
+                                  struct nix_bp_cfg_rsp *rsp)
+{
+       return nix_bp_enable(rvu, req, rsp, false);
+}
+
+int rvu_mbox_handler_nix_cpt_bp_enable(struct rvu *rvu,
+                                      struct nix_bp_cfg_req *req,
+                                      struct nix_bp_cfg_rsp *rsp)
+{
+       return nix_bp_enable(rvu, req, rsp, true);
+}
+
 static void nix_setup_lso_tso_l3(struct rvu *rvu, int blkaddr,
                                 u64 format, bool v4, u64 *fidx)
 {

diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
index 971115a5d2cc005e452afa6c3bd42316085bc923..4c8774899eaf5a04f3f3f2c5ed6d93e573049215 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
@@ -17,6 +17,11 @@
 #include "otx2_struct.h"
 #include "cn10k.h"
 
+static bool otx2_is_pfc_enabled(struct otx2_nic *pfvf)
+{
+       return IS_ENABLED(CONFIG_DCB) && !!pfvf->pfc_en;
+}
+
 static void otx2_nix_rq_op_stats(struct queue_stats *stats,
                                 struct otx2_nic *pfvf, int qidx)
 {
@@ -1723,18 +1728,43 @@ int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable)
                return -ENOMEM;
 
        req->chan_base = 0;
-#ifdef CONFIG_DCB
-       req->chan_cnt = pfvf->pfc_en ? IEEE_8021QAZ_MAX_TCS : 1;
-       req->bpid_per_chan = pfvf->pfc_en ? 1 : 0;
-#else
-       req->chan_cnt =  1;
-       req->bpid_per_chan = 0;
-#endif
+       if (otx2_is_pfc_enabled(pfvf)) {
+               req->chan_cnt = IEEE_8021QAZ_MAX_TCS;
+               req->bpid_per_chan = 1;
+       } else {
+               req->chan_cnt = 1;
+               req->bpid_per_chan = 0;
+       }
 
        return otx2_sync_mbox_msg(&pfvf->mbox);
 }
 EXPORT_SYMBOL(otx2_nix_config_bp);
 
+int otx2_nix_cpt_config_bp(struct otx2_nic *pfvf, bool enable)
+{
+       struct nix_bp_cfg_req *req;
+
+       if (enable)
+               req = otx2_mbox_alloc_msg_nix_cpt_bp_enable(&pfvf->mbox);
+       else
+               req = otx2_mbox_alloc_msg_nix_cpt_bp_disable(&pfvf->mbox);
+
+       if (!req)
+               return -ENOMEM;
+
+       req->chan_base = 0;
+       if (otx2_is_pfc_enabled(pfvf)) {
+               req->chan_cnt = IEEE_8021QAZ_MAX_TCS;
+               req->bpid_per_chan = 1;
+       } else {
+               req->chan_cnt = 1;
+               req->bpid_per_chan = 0;
+       }
+
+       return otx2_sync_mbox_msg(&pfvf->mbox);
+}
+EXPORT_SYMBOL(otx2_nix_cpt_config_bp);
+
 /* Mbox message handlers */
 void mbox_handler_cgx_stats(struct otx2_nic *pfvf,
                            struct cgx_stats_rsp *rsp)

diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
index bb78d825046de19cbca23b0ce5d34b6babeeb6ca..37a32ac0dae755dd4f9dbdc13d08f5162ee0ab9d 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
@@ -985,6 +985,7 @@ int otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool,
 int otx2_rxtx_enable(struct otx2_nic *pfvf, bool enable);
 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa);
 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable);
+int otx2_nix_cpt_config_bp(struct otx2_nic *pfvf, bool enable);
 void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, int qidx);
 void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq);
 int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura);

diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_dcbnl.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_dcbnl.c
index 294fba58b670954855a4c9ed18ea1e2095b54a8e..f110dfa423605d980e4365016fbeff2afa5ba6f4 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_dcbnl.c
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_dcbnl.c
@@ -435,6 +435,9 @@ process_pfc:
                return err;
        }
 
+       /* Default disable backpressure on NIX-CPT */
+       otx2_nix_cpt_config_bp(pfvf, false);
+
        /* Request Per channel Bpids */
        if (pfc->pfc_en)
                otx2_nix_config_bp(pfvf, true);

diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
index e310f99b1736616ac4eba38a2b1391a7f58a265a..8ec0296dee84b35fc912583a35d26b24a5413809 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
@@ -1551,6 +1551,9 @@ int otx2_init_hw_resources(struct otx2_nic *pf)
        if (err)
                goto err_free_npa_lf;
 
+       /* Default disable backpressure on NIX-CPT */
+       otx2_nix_cpt_config_bp(pf, false);
+
        /* Enable backpressure for CGX mapped PF/VFs */
        if (!is_otx2_lbkvf(pf->pdev))
                otx2_nix_config_bp(pf, true);