arm64: dts: qcom: sm8350: Add snps,dis_u3_susphy_quirk

During device mode initialization on certain QC targets, before the
runstop bit is set, sometimes it's observed that the GEVNTADR{LO/HI}
register write fails. As a result, GEVTADDR registers are still 0x0.
Upon setting runstop bit, DWC3 controller attempts to write the new
events to address 0x0, causing an SMMU fault and system crash.

This was initially observed on SM8450 and later reported on few
other targets as well. As suggested by Qualcomm HW team, clearing
the GUSB3PIPECTL.SUSPHY bit resolves the issue by preventing register
write failures. Address this by setting the snps,dis_u3_susphy_quirk
to keep the GUSB3PIPECTL.SUSPHY bit cleared. This change was tested
on multiple targets (SM8350, SM8450 QCS615 etc.) for over an year
and hasn't exhibited any side effects.

Signed-off-by: Prashanth K <prashanth.k@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250325123019.597976-3-prashanth.k@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 279a68a7146e4e71d31944c37465c2bfc6dec3a9..04a30df4362b65594c073b758f25bf2ae0398541 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -2652,6 +2652,7 @@
                                interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
                                iommus = <&apps_smmu 0x0 0x0>;
                                snps,dis_u2_susphy_quirk;
+                               snps,dis_u3_susphy_quirk;
                                snps,dis_enblslpm_quirk;
                                snps,dis-u1-entry-quirk;
                                snps,dis-u2-entry-quirk;
@@ -2730,6 +2731,7 @@
                                interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
                                iommus = <&apps_smmu 0x20 0x0>;
                                snps,dis_u2_susphy_quirk;
+                               snps,dis_u3_susphy_quirk;
                                snps,dis_enblslpm_quirk;
                                snps,dis-u1-entry-quirk;
                                snps,dis-u2-entry-quirk;