arm64: dts: qcom: ipq5332: add support for the RDP442 variant

Add the initial device tree support for the Reference Design
Platform(RDP) 442 based on IPQ5332 family of SoC. This patch carries
the support for Console UART, SPI NOR, eMMC and I2C.

Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230509160133.3794-3-quic_kathirav@quicinc.com

diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 4a2e09ec381da465866068b6a41a0c0395f79905..1ad68b728f50e33217aec95da2d3356f1d730741 100644 (file)
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -5,6 +5,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb
 dtb-$(CONFIG_ARCH_QCOM)        += apq8096-db820c.dtb
 dtb-$(CONFIG_ARCH_QCOM)        += apq8096-ifc6640.dtb
 dtb-$(CONFIG_ARCH_QCOM)        += ipq5332-mi01.2.dtb
+dtb-$(CONFIG_ARCH_QCOM)        += ipq5332-rdp442.dtb
 dtb-$(CONFIG_ARCH_QCOM)        += ipq5332-rdp468.dtb
 dtb-$(CONFIG_ARCH_QCOM)        += ipq6018-cp01-c1.dtb
 dtb-$(CONFIG_ARCH_QCOM)        += ipq8074-hk01.dtb

diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts
new file mode 100644 (file)
index 0000000..bcf3b31
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * IPQ5332 RDP442 board device tree source
+ *
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "ipq5332.dtsi"
+
+/ {
+       model = "Qualcomm Technologies, Inc. IPQ5332 MI01.3";
+       compatible = "qcom,ipq5332-ap-mi01.3", "qcom,ipq5332";
+
+       aliases {
+               serial0 = &blsp1_uart0;
+       };
+
+       chosen {
+               stdout-path = "serial0";
+       };
+};
+
+&blsp1_uart0 {
+       pinctrl-0 = <&serial_0_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+};
+
+&blsp1_i2c1 {
+       clock-frequency  = <400000>;
+       pinctrl-0 = <&i2c_1_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+};
+
+&blsp1_spi0 {
+       pinctrl-0 = <&spi_0_data_clk_pins &spi_0_cs_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+
+       flash@0 {
+               compatible = "micron,n25q128a11", "jedec,spi-nor";
+               reg = <0>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               spi-max-frequency = <50000000>;
+       };
+};
+
+&sdhc {
+       bus-width = <4>;
+       max-frequency = <192000000>;
+       mmc-ddr-1_8v;
+       mmc-hs200-1_8v;
+       non-removable;
+       pinctrl-0 = <&sdc_default_state>;
+       pinctrl-names = "default";
+       status = "okay";
+};
+
+&sleep_clk {
+       clock-frequency = <32000>;
+};
+
+&xo_board {
+       clock-frequency = <24000000>;
+};
+
+/* PINCTRL */
+
+&tlmm {
+       i2c_1_pins: i2c-1-state {
+               pins = "gpio29", "gpio30";
+               function = "blsp1_i2c0";
+               drive-strength = <8>;
+               bias-pull-up;
+       };
+
+       sdc_default_state: sdc-default-state {
+               clk-pins {
+                       pins = "gpio13";
+                       function = "sdc_clk";
+                       drive-strength = <8>;
+                       bias-disable;
+               };
+
+               cmd-pins {
+                       pins = "gpio12";
+                       function = "sdc_cmd";
+                       drive-strength = <8>;
+                       bias-pull-up;
+               };
+
+               data-pins {
+                       pins = "gpio8", "gpio9", "gpio10", "gpio11";
+                       function = "sdc_data";
+                       drive-strength = <8>;
+                       bias-pull-up;
+               };
+       };
+
+       spi_0_data_clk_pins: spi-0-data-clk-state {
+               pins = "gpio14", "gpio15", "gpio16";
+               function = "blsp0_spi";
+               drive-strength = <2>;
+               bias-pull-down;
+       };
+
+       spi_0_cs_pins: spi-0-cs-state {
+               pins = "gpio17";
+               function = "blsp0_spi";
+               drive-strength = <2>;
+               bias-pull-up;
+       };
+};