drm/xe/dsb: DSB implementation for xe
authorAnimesh Manna <animesh.manna@intel.com>
Fri, 1 Dec 2023 09:14:05 +0000 (14:44 +0530)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Thu, 21 Dec 2023 16:45:10 +0000 (11:45 -0500)
Add xe specific DSB buffer handling methods.

v1: Initial version.
v2: Add null check after dynamic memory allocation of vma. [Uma]

Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
drivers/gpu/drm/xe/Makefile
drivers/gpu/drm/xe/display/xe_dsb_buffer.c [new file with mode: 0644]

index b8ad42fcbea2a67d9a6d6a1ddacda644ea7e9e8e..e6f98d80778393dc953b2af3b36eac5c4aeb8333 100644 (file)
@@ -166,6 +166,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
        display/xe_plane_initial.o \
        display/xe_display_rps.o \
        display/xe_display_misc.o \
+       display/xe_dsb_buffer.o \
        display/intel_fbdev_fb.o \
        display/intel_fb_bo.o \
        display/ext/i915_irq.o \
diff --git a/drivers/gpu/drm/xe/display/xe_dsb_buffer.c b/drivers/gpu/drm/xe/display/xe_dsb_buffer.c
new file mode 100644 (file)
index 0000000..27c2fb1
--- /dev/null
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2023, Intel Corporation.
+ */
+
+#include "i915_drv.h"
+#include "i915_vma.h"
+#include "intel_display_types.h"
+#include "intel_dsb_buffer.h"
+#include "xe_bo.h"
+#include "xe_gt.h"
+
+u32 intel_dsb_buffer_ggtt_offset(struct intel_dsb_buffer *dsb_buf)
+{
+       return xe_bo_ggtt_addr(dsb_buf->vma->bo);
+}
+
+void intel_dsb_buffer_write(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val)
+{
+       iosys_map_wr(&dsb_buf->vma->bo->vmap, idx * 4, u32, val);
+}
+
+u32 intel_dsb_buffer_read(struct intel_dsb_buffer *dsb_buf, u32 idx)
+{
+       return iosys_map_rd(&dsb_buf->vma->bo->vmap, idx * 4, u32);
+}
+
+void intel_dsb_buffer_memset(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val, size_t size)
+{
+       WARN_ON(idx > (dsb_buf->buf_size - size) / sizeof(*dsb_buf->cmd_buf));
+
+       iosys_map_memset(&dsb_buf->vma->bo->vmap, idx * 4, val, size);
+}
+
+bool intel_dsb_buffer_create(struct intel_crtc *crtc, struct intel_dsb_buffer *dsb_buf, size_t size)
+{
+       struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+       struct drm_i915_gem_object *obj;
+       struct i915_vma *vma;
+
+       vma = kzalloc(sizeof(*vma), GFP_KERNEL);
+       if (!vma)
+               return false;
+
+       obj = xe_bo_create_pin_map(i915, xe_device_get_root_tile(i915),
+                                  NULL, PAGE_ALIGN(size),
+                                  ttm_bo_type_kernel,
+                                  XE_BO_CREATE_VRAM_IF_DGFX(xe_device_get_root_tile(i915)) |
+                                  XE_BO_CREATE_GGTT_BIT);
+       if (IS_ERR(obj)) {
+               kfree(vma);
+               return false;
+       }
+
+       vma->bo = obj;
+       dsb_buf->vma = vma;
+       dsb_buf->buf_size = size;
+
+       return true;
+}
+
+void intel_dsb_buffer_cleanup(struct intel_dsb_buffer *dsb_buf)
+{
+       xe_bo_unpin_map_no_vm(dsb_buf->vma->bo);
+       kfree(dsb_buf->vma);
+}
+
+void intel_dsb_buffer_flush_map(struct intel_dsb_buffer *dsb_buf)
+{
+       /* TODO: add xe specific flush_map() for dsb buffer object. */
+}