drm/bridge: tc358767: Use tc_pxl_pll_calc() to correct adjusted_mode clock

Use tc_pxl_pll_calc() to find out the exact clock frequency generated by the
Pixel PLL. Use the Pixel PLL frequency as adjusted_mode clock frequency and
pass it down the display pipeline to obtain exactly this frequency on input
into this bridge.

The precise input frequency that matches the Pixel PLL frequency is
important for this bridge, as if the frequencies do not match, the
bridge does suffer VFIFO overruns or underruns.

Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Robert Foss <rfoss@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20240625120334.145320-2-marex@denx.de

diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
index a2d073e4856f319556d859c75a03156700548aa3..a10f4c21337e48480b8dfd8cbe5abf5ac0a07b85 100644 (file)
--- a/drivers/gpu/drm/bridge/tc358767.c
+++ b/drivers/gpu/drm/bridge/tc358767.c
@@ -1624,6 +1624,18 @@ static int tc_dpi_atomic_check(struct drm_bridge *bridge,
                               struct drm_crtc_state *crtc_state,
                               struct drm_connector_state *conn_state)
 {
+       struct tc_data *tc = bridge_to_tc(bridge);
+       int adjusted_clock = 0;
+       int ret;
+
+       ret = tc_pxl_pll_calc(tc, clk_get_rate(tc->refclk),
+                             crtc_state->mode.clock * 1000,
+                             &adjusted_clock, NULL);
+       if (ret)
+               return ret;
+
+       crtc_state->adjusted_mode.clock = adjusted_clock / 1000;
+
        /* DSI->DPI interface clock limitation: upto 100 MHz */
        if (crtc_state->adjusted_mode.clock > 100000)
                return -EINVAL;
@@ -1636,6 +1648,18 @@ static int tc_edp_atomic_check(struct drm_bridge *bridge,
                               struct drm_crtc_state *crtc_state,
                               struct drm_connector_state *conn_state)
 {
+       struct tc_data *tc = bridge_to_tc(bridge);
+       int adjusted_clock = 0;
+       int ret;
+
+       ret = tc_pxl_pll_calc(tc, clk_get_rate(tc->refclk),
+                             crtc_state->mode.clock * 1000,
+                             &adjusted_clock, NULL);
+       if (ret)
+               return ret;
+
+       crtc_state->adjusted_mode.clock = adjusted_clock / 1000;
+
        /* DPI->(e)DP interface clock limitation: upto 154 MHz */
        if (crtc_state->adjusted_mode.clock > 154000)
                return -EINVAL;