ARM: 8989/1: use .fpu assembler directives instead of assembler arguments

Explicit FPU selection has been introduced in commit 1a6be26d5b1a
("[ARM] Enable VFP to be built when non-VFP capable CPUs are selected")
to make use of assembler mnemonics for VFP instructions.

However, clang currently does not support passing assembler flags
like this and errors out with:
clang-10: error: the clang compiler does not support '-Wa,-mfpu=softvfp+vfp'

Make use of the .fpu assembler directives to select the floating point
hardware selectively. Also use the new unified assembler language
mnemonics. This allows to build these procedures with Clang.

Link: https://github.com/ClangBuiltLinux/linux/issues/762
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>

diff --git a/arch/arm/vfp/Makefile b/arch/arm/vfp/Makefile
index 9975b63ac3b0de410f4cab98f3d2bfe3e3035d68..749901a72d6dc6c4beffddc464a41ba0a5173e8a 100644 (file)
--- a/arch/arm/vfp/Makefile
+++ b/arch/arm/vfp/Makefile
@@ -8,6 +8,4 @@
 # ccflags-y := -DDEBUG
 # asflags-y := -DDEBUG
 
-KBUILD_AFLAGS  :=$(KBUILD_AFLAGS:-msoft-float=-Wa,-mfpu=softvfp+vfp -mfloat-abi=soft)
-
 obj-y          += vfpmodule.o entry.o vfphw.o vfpsingle.o vfpdouble.o

diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S
index b2e560290860e23ea7062c5f03e91ae150f243eb..29ed36b99d1d77ccc8678fb84557fcdb632d1cd8 100644 (file)
--- a/arch/arm/vfp/vfphw.S
+++ b/arch/arm/vfp/vfphw.S
@@ -258,11 +258,14 @@ vfp_current_hw_state_address:
 
 ENTRY(vfp_get_float)
        tbl_branch r0, r3, #3
+       .fpu    vfpv2
        .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-1:     mrc     p10, 0, r0, c\dr, c0, 0 @ fmrs  r0, s0
+1:     vmov    r0, s\dr
        ret     lr
        .org    1b + 8
-1:     mrc     p10, 0, r0, c\dr, c0, 4 @ fmrs  r0, s1
+       .endr
+       .irp    dr,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
+1:     vmov    r0, s\dr
        ret     lr
        .org    1b + 8
        .endr
@@ -270,11 +273,14 @@ ENDPROC(vfp_get_float)
 
 ENTRY(vfp_put_float)
        tbl_branch r1, r3, #3
+       .fpu    vfpv2
        .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-1:     mcr     p10, 0, r0, c\dr, c0, 0 @ fmsr  r0, s0
+1:     vmov    s\dr, r0
        ret     lr
        .org    1b + 8
-1:     mcr     p10, 0, r0, c\dr, c0, 4 @ fmsr  r0, s1
+       .endr
+       .irp    dr,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
+1:     vmov    s\dr, r0
        ret     lr
        .org    1b + 8
        .endr
@@ -282,15 +288,17 @@ ENDPROC(vfp_put_float)
 
 ENTRY(vfp_get_double)
        tbl_branch r0, r3, #3
+       .fpu    vfpv2
        .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-1:     fmrrd   r0, r1, d\dr
+1:     vmov    r0, r1, d\dr
        ret     lr
        .org    1b + 8
        .endr
 #ifdef CONFIG_VFPv3
        @ d16 - d31 registers
-       .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-1:     mrrc    p11, 3, r0, r1, c\dr    @ fmrrd r0, r1, d\dr
+       .fpu    vfpv3
+       .irp    dr,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
+1:     vmov    r0, r1, d\dr
        ret     lr
        .org    1b + 8
        .endr
@@ -304,15 +312,17 @@ ENDPROC(vfp_get_double)
 
 ENTRY(vfp_put_double)
        tbl_branch r2, r3, #3
+       .fpu    vfpv2
        .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-1:     fmdrr   d\dr, r0, r1
+1:     vmov    d\dr, r0, r1
        ret     lr
        .org    1b + 8
        .endr
 #ifdef CONFIG_VFPv3
+       .fpu    vfpv3
        @ d16 - d31 registers
-       .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-1:     mcrr    p11, 3, r0, r1, c\dr    @ fmdrr r0, r1, d\dr
+       .irp    dr,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
+1:     vmov    d\dr, r0, r1
        ret     lr
        .org    1b + 8
        .endr