drm/amdgpu: Clean up GFX v9.4.3 IP version checks

Remove unnecessary IP version checks for GFX 9.4.3 and similar variants.
Wrap checks inside meaningful function.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Asad Kamal <asad.kamal@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index 2ba185875baa996453f202cda55aa161225a1f6d..f4635fc8a7ca48cd2fe5c3e48313712832a1642f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -942,21 +942,12 @@ static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev)
        adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs;
        adev->gfx.ras = &gfx_v9_4_3_ras;
 
-       switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
-       case IP_VERSION(9, 4, 3):
-       case IP_VERSION(9, 4, 4):
-       case IP_VERSION(9, 5, 0):
-               adev->gfx.config.max_hw_contexts = 8;
-               adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
-               adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
-               adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
-               adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
-               gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0), regGB_ADDR_CONFIG);
-               break;
-       default:
-               BUG();
-               break;
-       }
+       adev->gfx.config.max_hw_contexts = 8;
+       adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
+       adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
+       adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
+       adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
+       gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0), regGB_ADDR_CONFIG);
 
        adev->gfx.config.gb_addr_config = gb_addr_config;
 
@@ -2795,16 +2786,10 @@ static int gfx_v9_4_3_set_clockgating_state(struct amdgpu_ip_block *ip_block,
                return 0;
 
        num_xcc = NUM_XCC(adev->gfx.xcc_mask);
-       switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
-       case IP_VERSION(9, 4, 3):
-       case IP_VERSION(9, 4, 4):
-               for (i = 0; i < num_xcc; i++)
-                       gfx_v9_4_3_xcc_update_gfx_clock_gating(
-                               adev, state == AMD_CG_STATE_GATE, i);
-               break;
-       default:
-               break;
-       }
+       for (i = 0; i < num_xcc; i++)
+               gfx_v9_4_3_xcc_update_gfx_clock_gating(
+                       adev, state == AMD_CG_STATE_GATE, i);
+
        return 0;
 }
 
@@ -4867,34 +4852,13 @@ static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev)
 
 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev)
 {
-       /* init asci gds info */
-       switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
-       case IP_VERSION(9, 4, 3):
-       case IP_VERSION(9, 4, 4):
-       case IP_VERSION(9, 5, 0):
-               /* 9.4.3 removed all the GDS internal memory,
-                * only support GWS opcode in kernel, like barrier
-                * semaphore.etc */
-               adev->gds.gds_size = 0;
-               break;
-       default:
-               adev->gds.gds_size = 0x10000;
-               break;
-       }
-
-       switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
-       case IP_VERSION(9, 4, 3):
-       case IP_VERSION(9, 4, 4):
-       case IP_VERSION(9, 5, 0):
-               /* deprecated for 9.4.3, no usage at all */
-               adev->gds.gds_compute_max_wave_id = 0;
-               break;
-       default:
-               /* this really depends on the chip */
-               adev->gds.gds_compute_max_wave_id = 0x7ff;
-               break;
-       }
+       /* 9.4.3 variants removed all the GDS internal memory,
+        * only support GWS opcode in kernel, like barrier
+        * semaphore.etc */
 
+       /* init asic gds info */
+       adev->gds.gds_size = 0;
+       adev->gds.gds_compute_max_wave_id = 0;
        adev->gds.gws_size = 64;
        adev->gds.oa_size = 16;
 }

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
index 5470cef7e9bd172eea2f933365551ae40695d920..cb25f7f0dfc1ccffc77e9b4b941476321545f703 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
@@ -313,6 +313,16 @@ gfxhub_v1_2_xcc_disable_identity_aperture(struct amdgpu_device *adev,
        }
 }
 
+static inline bool
+gfxhub_v1_2_per_process_xnack_support(struct amdgpu_device *adev)
+{
+       /*
+        * TODO: Check if this function is really needed, so far only 9.4.3
+        * variants use GFXHUB 1.2
+        */
+       return !!adev->aid_mask;
+}
+
 static void gfxhub_v1_2_xcc_setup_vmid_config(struct amdgpu_device *adev,
                                              uint32_t xcc_mask)
 {
@@ -355,7 +365,7 @@ static void gfxhub_v1_2_xcc_setup_vmid_config(struct amdgpu_device *adev,
                                            PAGE_TABLE_BLOCK_SIZE,
                                            block_size);
                        /* Send no-retry XNACK on fault to suppress VM fault storm.
-                        * On 9.4.2 and 9.4.3, XNACK can be enabled in
+                        * On 9.4.3 variants, XNACK can be enabled in
                         * the SQ per-process.
                         * Retry faults need to be enabled for that to work.
                         */
@@ -363,14 +373,8 @@ static void gfxhub_v1_2_xcc_setup_vmid_config(struct amdgpu_device *adev,
                                tmp, VM_CONTEXT1_CNTL,
                                RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
                                !adev->gmc.noretry ||
-                                       amdgpu_ip_version(adev, GC_HWIP, 0) ==
-                                               IP_VERSION(9, 4, 2) ||
-                                       amdgpu_ip_version(adev, GC_HWIP, 0) ==
-                                               IP_VERSION(9, 4, 3) ||
-                                       amdgpu_ip_version(adev, GC_HWIP, 0) ==
-                                               IP_VERSION(9, 4, 4) ||
-                                       amdgpu_ip_version(adev, GC_HWIP, 0) ==
-                                               IP_VERSION(9, 5, 0));
+                                       gfxhub_v1_2_per_process_xnack_support(
+                                               adev));
                        WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_CONTEXT1_CNTL,
                                            i * hub->ctx_distance, tmp);
                        WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),