drm/msm: Fix order of selector programming in cluster snapshot

Program the selector _after_ selecting the aperture.  This aligns with
the downstream driver, and fixes a case where we were failing to capture
ctx0 regs (and presumably what we thought were ctx1 regs were actually
ctx0).

Suggested-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/666655/

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
index 8420cbe129c06663813a1c51acf80020e5d72dea..b4c8583dd6caafb11b8d295e00fac144d39d133f 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
@@ -759,15 +759,15 @@ static void a7xx_get_cluster(struct msm_gpu *gpu,
        size_t datasize;
        int i, regcount = 0;
 
-       /* Some clusters need a selector register to be programmed too */
-       if (cluster->sel)
-               in += CRASHDUMP_WRITE(in, cluster->sel->cd_reg, cluster->sel->val);
-
        in += CRASHDUMP_WRITE(in, REG_A7XX_CP_APERTURE_CNTL_CD,
                A7XX_CP_APERTURE_CNTL_CD_PIPE(cluster->pipe_id) |
                A7XX_CP_APERTURE_CNTL_CD_CLUSTER(cluster->cluster_id) |
                A7XX_CP_APERTURE_CNTL_CD_CONTEXT(cluster->context_id));
 
+       /* Some clusters need a selector register to be programmed too */
+       if (cluster->sel)
+               in += CRASHDUMP_WRITE(in, cluster->sel->cd_reg, cluster->sel->val);
+
        for (i = 0; cluster->regs[i] != UINT_MAX; i += 2) {
                int count = RANGE(cluster->regs, i);