ice: Add 'Execute Pending LLDP MIB' Admin Queue command
authorTsotne Chakhvadze <tsotne.chakhvadze@intel.com>
Wed, 24 Aug 2022 12:07:27 +0000 (14:07 +0200)
committerTony Nguyen <anthony.l.nguyen@intel.com>
Thu, 19 Jan 2023 16:18:03 +0000 (08:18 -0800)
In DCB Willing Mode (FW managed LLDP), when the link partner changes
configuration which requires fewer TCs, the TCs that are no longer
needed are suspended by EMP FW, removed, and never resumed. This occurs
before a MIB change event is indicated to SW. The permanent suspension and
removal of these TC nodes in the scheduler prevents RDMA from being able
to destroy QPs associated with this TC, requiring a CORE reset to recover.

A new DCBX configuration change flow is defined to allow SW driver and
other SW components (RDMA) to properly adjust to the configuration
changes before they are taking effect in HW. This flow includes a
two-way handshake between EMP FW<->LAN SW<->RDMA SW.

List of changes:
- Add 'Execute Pending LLDP MIB' AQC.
- Add 'Pending Event Enable' bit.
- Add additional logic to ignore Pending Event Enable' request
  while 'LLDP MIB Chnage' event is disabled.
- Add 'Execute Pending LLDP MIB' AQC sending function to FW,
  which is needed to take place MIB Event change.

Signed-off-by: Tsotne Chakhvadze <tsotne.chakhvadze@intel.com>
Co-developed-by: Karen Sornek <karen.sornek@intel.com>
Signed-off-by: Karen Sornek <karen.sornek@intel.com>
Co-developed-by: Dave Ertman <david.m.ertman@intel.com>
Signed-off-by: Dave Ertman <david.m.ertman@intel.com>
Co-developed-by: Anatolii Gerasymenko <anatolii.gerasymenko@intel.com>
Signed-off-by: Anatolii Gerasymenko <anatolii.gerasymenko@intel.com>
Tested-by: Arpana Arland <arpanax.arland@intel.com> (A Contingent worker at Intel)
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
drivers/net/ethernet/intel/ice/ice_common.c
drivers/net/ethernet/intel/ice/ice_common.h
drivers/net/ethernet/intel/ice/ice_dcb.c

index 958c1e4352321cc5008c16dbe485f08847023483..838d9b274d6854f0df659b36010e55604a5602ea 100644 (file)
@@ -1659,14 +1659,24 @@ struct ice_aqc_lldp_get_mib {
 #define ICE_AQ_LLDP_TX_ACTIVE                  0
 #define ICE_AQ_LLDP_TX_SUSPENDED               1
 #define ICE_AQ_LLDP_TX_FLUSHED                 3
+/* DCBX mode */
+#define ICE_AQ_LLDP_DCBX_M                     GENMASK(7, 6)
+#define ICE_AQ_LLDP_DCBX_NA                    0
+#define ICE_AQ_LLDP_DCBX_CEE                   1
+#define ICE_AQ_LLDP_DCBX_IEEE                  2
+
+       u8 state;
+#define ICE_AQ_LLDP_MIB_CHANGE_STATE_M         BIT(0)
+#define ICE_AQ_LLDP_MIB_CHANGE_EXECUTED                0
+#define ICE_AQ_LLDP_MIB_CHANGE_PENDING         1
+
 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00)
  * and in the LLDP MIB Change Event (0x0A01). They are valid for the
  * Get LLDP MIB (0x0A00) response only.
  */
-       u8 reserved1;
        __le16 local_len;
        __le16 remote_len;
-       u8 reserved2[2];
+       u8 reserved[2];
        __le32 addr_high;
        __le32 addr_low;
 };
@@ -1677,6 +1687,9 @@ struct ice_aqc_lldp_set_mib_change {
        u8 command;
 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE          0x0
 #define ICE_AQ_LLDP_MIB_UPDATE_DIS             0x1
+#define ICE_AQ_LLDP_MIB_PENDING_M              BIT(1)
+#define ICE_AQ_LLDP_MIB_PENDING_DISABLE                0
+#define ICE_AQ_LLDP_MIB_PENDING_ENABLE         1
        u8 reserved[15];
 };
 
@@ -2329,6 +2342,7 @@ enum ice_adminq_opc {
        ice_aqc_opc_lldp_set_local_mib                  = 0x0A08,
        ice_aqc_opc_lldp_stop_start_specific_agent      = 0x0A09,
        ice_aqc_opc_lldp_filter_ctrl                    = 0x0A0A,
+       ice_aqc_opc_lldp_execute_pending_mib            = 0x0A0B,
 
        /* RSS commands */
        ice_aqc_opc_set_rss_key                         = 0x0B02,
index d02b55b6aa9cf03ed233db06ab1c0eefe64e728e..f5842ff42bc7145950e7a29f1d7f09230ef0e0b4 100644 (file)
@@ -5503,6 +5503,19 @@ ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add)
        return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
 }
 
+/**
+ * ice_lldp_execute_pending_mib - execute LLDP pending MIB request
+ * @hw: pointer to HW struct
+ */
+int ice_lldp_execute_pending_mib(struct ice_hw *hw)
+{
+       struct ice_aq_desc desc;
+
+       ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_execute_pending_mib);
+
+       return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
+}
+
 /**
  * ice_fw_supports_report_dflt_cfg
  * @hw: pointer to the hardware structure
index 4c6a0b5c93044cc4a5262253269ff055e34fb2d9..22839c4f7247fb6fc9e271f365abc16babf7b0cd 100644 (file)
@@ -221,6 +221,7 @@ ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw);
 int
 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add);
+int ice_lldp_execute_pending_mib(struct ice_hw *hw);
 int
 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
                u16 bus_addr, __le16 addr, u8 params, u8 *data,
index 6be02f9b0b8c25b777e6c2ee0ca91f110bff8d33..22a94e05233a57860bacd62cff6f9077f79e2398 100644 (file)
@@ -73,6 +73,9 @@ ice_aq_cfg_lldp_mib_change(struct ice_hw *hw, bool ena_update,
 
        if (!ena_update)
                cmd->command |= ICE_AQ_LLDP_MIB_UPDATE_DIS;
+       else
+               cmd->command |= FIELD_PREP(ICE_AQ_LLDP_MIB_PENDING_M,
+                                          ICE_AQ_LLDP_MIB_PENDING_ENABLE);
 
        return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
 }