drm/amdgpu/gfx12: split userq setup to a separate switch

Add a separate switch statement for the userq callback
assignment so that we can assign the callbacks for each
asic as the firmware becomes available.

Reviewed-by: Sunil Khatri <sunil.khatri@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index 1c7022103c63848baed80a424f86549a2098a472..bbc6349e5270e77a5567a224a713b120d373c39b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -1402,6 +1402,20 @@ static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
                adev->gfx.mec.num_mec = 1;
                adev->gfx.mec.num_pipe_per_mec = 2;
                adev->gfx.mec.num_queue_per_pipe = 4;
+               break;
+       default:
+               adev->gfx.me.num_me = 1;
+               adev->gfx.me.num_pipe_per_me = 1;
+               adev->gfx.me.num_queue_per_pipe = 1;
+               adev->gfx.mec.num_mec = 1;
+               adev->gfx.mec.num_pipe_per_mec = 4;
+               adev->gfx.mec.num_queue_per_pipe = 8;
+               break;
+       }
+
+       switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
+       case IP_VERSION(12, 0, 0):
+       case IP_VERSION(12, 0, 1):
 #ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
                /* add firmware version checks here */
                if (0) {
@@ -1411,12 +1425,6 @@ static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
 #endif
                break;
        default:
-               adev->gfx.me.num_me = 1;
-               adev->gfx.me.num_pipe_per_me = 1;
-               adev->gfx.me.num_queue_per_pipe = 1;
-               adev->gfx.mec.num_mec = 1;
-               adev->gfx.mec.num_pipe_per_mec = 4;
-               adev->gfx.mec.num_queue_per_pipe = 8;
                break;
        }