clk: rockchip: mark aclk_emmc_noc as a critical clock on rk3399
authorXing Zheng <zhengxing@rock-chips.com>
Wed, 24 Aug 2016 18:29:39 +0000 (11:29 -0700)
committerHeiko Stuebner <heiko@sntech.de>
Wed, 24 Aug 2016 21:44:49 +0000 (23:44 +0200)
We don't have code to handle any of the noc clocks in rk3399 and they're
all just listed as critical clocks.  Let's do the same for
aclk_emmc_noc.

Without this clock being marked as critical we have problems around
suspend/resume after commit 20c389e656a8 ("clk: rockchip: fix incorrect
aclk_emmc source gate bits on rk3399").  Before that change we were
presumably not actually gating any of these clocks because we were
setting the wrong gate.

Fixes: 20c389e656a8 ("clk: rockchip: fix incorrect aclk_emmc source gate bits on rk3399")
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
drivers/clk/rockchip/clk-rk3399.c

index ec5b2fd77c5053769a29a81fc3fae25b51df5e2f..cdfabeb9a034c5fec840dc3c952a385b36536df5 100644 (file)
@@ -1484,6 +1484,7 @@ static const char *const rk3399_cru_critical_clocks[] __initconst = {
        "hclk_perilp1",
        "hclk_perilp1_noc",
        "aclk_dmac0_perilp",
+       "aclk_emmc_noc",
        "gpll_hclk_perilp1_src",
        "gpll_aclk_perilp0_src",
        "gpll_aclk_perihp_src",